Abstract: In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device.

Abstract: A method for making a self-aligned isolated memory core for a flash memory wafer includes the steps of establishing control gates for memory cells in the core by depositing a first polysilicon layer on a silicon substrate, etching the first layer, and depositing a second polysilicon layer on the substrate, with the polysilicon layers being separated by an interpoly dielectric layer. Then, after the control gates have been established, isolation trenches are formed in the silicon substrate between regions by self-aligned etching processes.

Abstract: Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely spaced apart non-volatile transistors and heating during and subsequent to deposition to complete flowing of the B- or BP-HDP oxide into and filling the undercut regions on the sidewall spacers and to densify the B- or BP-HDP oxide.

Abstract: A silicon oxide layer is deposited at a thickness of about 50 Å or less by a multi-stage method comprising depositing a sub-layer of silicon oxide in each stage by PECVD at a low deposition rate. Embodiments include depositing a silicon dioxide liner over a gate electrode in at least four stages, each stage comprising depositing a sub-layer at a thickness of 10 Å or less.

Abstract: A method for testing tunnel oxide on a memory-related structure. In one method embodiment, the present invention accesses a memory-related structure during a manufacturing process. Next, the present embodiment applies a constant voltage to a gate of the memory-related structure. The present embodiment then measures a first gate current for the memory-related structure when the constant voltage is initially applied, to obtain a first value. Next, the present embodiment measures a second gate current for the memory-related structure a period of time after the constant voltage is initially applied to obtain a second value. A calculation of ratio of the second value to the first value is then performed. The present embodiment then generates a graph of the first value and the ratio of the second value to the first value as a function of time, wherein a decrease in the graph signifies stress induced electron trapping behavior of the tunnel oxide.

Abstract: A method of using critical dimension measurements to control stepper process parameters is disclosed. In one illustrative embodiment, the method comprises forming a masking layer above a process layer, the masking layer having a plurality of features formed therein, measuring at least one critical dimension of a plurality of features positioned within at least one exposure field of a stepper exposure process used in forming the features, and determining a tilt of the masking layer within at least one exposure field based upon the measured critical dimensions of the plurality of features. In one illustrative embodiment, the system comprises a metrology tool adapted to measure at least one critical dimension of a plurality of features in a masking layer and a controller for determining a tilt of the masking layer based upon the measured critical dimensions of said plurality of features.

Abstract: A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

Abstract: A processor supports at least two different state save formats. Each format stores state in the form that the state exists in one or more operating modes of the processor. The operand size of the state save and state restore instructions may be used to indicate which state format is assumed by the processor during execution of the state save and state restore instructions. In one implementation, the processor implements a processor architecture compatible with the x86 architecture with enhancements to support 64 bit addressing and processing. In modes in which 64 bit addressing is supported, segmentation is not used. In 32 bit and 16 bit modes, segmentation is used. Thus, the address of a floating point instruction and/or operand may be indicated by a segment selector or pointer or by a pointer only.

Abstract: A novel switching device is provided with an active region arranged between first and second electrodes and including a molecular system and ionic complexes distributed in the system. A control electrode is provided for controlling an electric field applied to the active region, which switches between a high-impedance state and a low-impedance state when the electrical field having a predetermined polarity and intensity is applied for a predetermined time.

Abstract: Diffusion of As in SiGe of MOS transistors based on Si/SiGe is prevented by ion implanting boron. Embodiments include forming As source/drain extension implants in a strained Si/SiGe substrate, ion implanting boron at between the As source/drain extension implant junctions and subsequently annealing to activate the As source/drain extensions, thereby preventing distortion of the originally formed junction.

Abstract: A method for evaluating the effect of crystalline originated pits (COP's) in a silicon substrate on semiconductor devices method locates a first test structure created on a COP on the substrate and a second test structure created on the substrate but not on a COP. The electrical properties of the first and second test structure are then examined and compared. If there is a difference in their electrical properties, then the COP would affect a structure similar to the test structures of a semiconductor device. In this manner, the effects of COP's on the yield for the substrate can be understood.

Abstract: A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.

Abstract: A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.

Abstract: A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface coupled to the processor via an I/O link. The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor coupled to the I/O interface via a peripheral bus. The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.

Abstract: The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.

Abstract: A memory storage and retrieval device containing (a) an electrically conductive first electrode; (b) an electrically conductive second electrode; and (c) a layer stack intermediate the first and second electrodes containing (d) at least one active layer containing at least one polymer with variable electrical conductivity; and (e) at least one passive layer comprised of a material for varying the electrical conductivity of the at least one active layer upon application of an electrical potential difference between the first and second electrodes.

Abstract: A network switch includes a switching module and network switch ports connecting respective subnetworks. The switching module includes a plurality of address tables for storing address information (e.g., layer 2 and layer 3 address and switching information), where at least one table is configured for storing subnetwork identifiers of subnetworks that are reachable by the network switch.

Abstract: A method for filling an isolation trench structure during a semiconductor fabrication process is disclosed. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an oxide utilizing a biased high density plasma deposition process. In a preferred embodiment, the silicon-rich liner is an in-situ HDP liner having a thickness of between 100 and 400 Angstroms, and preferably 200 Angstroms. Depositing a silicon-rich liner on the trench surface prior to depositing the high density plasma oxide eliminates the formation of defects at the surface of the isolation trench structure. Thus, the quality of the oxide fill is improved, as is yield and device performance.

Abstract: According to an example embodiment of the present invention, a portion of substrate in the back side of a semiconductor chip is removed as a function of photons emitted through substrate remaining at the back side. The use of emitted photons is used to control the substrate removal process.

Abstract: Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.