Abstract: A digital rights management system includes an authentication module and a decryption module. If desired, the modules can be implemented in separate integrated circuits. The authentication module retrieves authentication information for protected content and powers down after the authentication information is retrieved. The decryption module decrypts the protected content based on the authentication information while the authentication module is powered down.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract: A digital processor for recovering a source bitstream from an encoded bitstream that has been encoded according to a context adaptive binary arithmetic coding (CABAC) algorithm. The processor includes a first execution unit and a second execution unit. The first execution unit generates first execution data by operating on a first register and a second register, and stores the first execution data in the first register. The first execution data includes a current output bit, a temporary range value and a temporary offset value. The current output bit corresponds to a bit of the source bitstream. The second execution unit generates second execution data by operating on the first register and the second register, and stores the second execution data in the second register. The second execution data includes a normalized range value and a normalized offset value.

Abstract: A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) sends a garbage collection request and a first log to a special processing unit (SPU). The first log includes an address and a data size of each allocated data object stored in a heap in memory corresponding to the CPU. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU efficiently performs operations of a garbage collection algorithm due to its architecture on a local representation of the data objects stored in the memory. The SPU records a list of changes it performs to remove dead data objects and compact live data objects. This list is subsequently sent to the CPU, which performs the included operations.

Abstract: A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector receives a first rise edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the rise edge has passed through the delay line, and in response, sends the injector a second trigger to send a next single fall edge of the clock input signal to the delay line. A charge pump determines a timing difference between the delay edge signal and a reference edge signal sent from the injector. The charge pump sends the control signal to the delay line to adjust the delay setting of the delay line based on the timing difference.

Abstract: A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.

Abstract: A cable solution which enables a flash controller which is located on a motherboard of an information processing system to be coupled with a memory socket which is located within a passive socket panel. In certain embodiments, a cable and header arrangement is provided for connecting the motherboard to the chassis socket panel card. This arrangement allows the front panel card to be simplified (i.e., to be a passive card). In certain embodiments, the solution uses a cable structure such as that used for integrated drive electronics (IDE) type disk drive cables or an ultra AT attachment (U-ATA) type cable. The cable solution provides a low cost solution which offers multiple performance options for a single cost. For example, the cable solution functions with both a standard memory card socket as well as a high speed memory card. Also, in certain embodiments, the header connections include ground signal paths interposed among the data signal paths.

Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Abstract: A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.

Abstract: Embodiments of systems and methods for improved measurement of transient thermal responses in electronic systems are described herein. Embodiments of the disclosure use the known thermal transfer function of an electronic system to generate an equivalent resistor-capacitor (RC) network having a dynamic response that is identical to a given power excitation as the actual electronic system would have to that power excitation. Using the analogy between thermal and electrical systems, a Foster RC network is constructed, comprising a plurality of RC stages in which resistors and capacitors are connected in parallel. Subsequently, the analog thermal RC network is converted into an infinite impulse response (IIR) digital filter, whose coefficients can be obtained the Z-transform of the analog thermal RC network. This IIR digital filter establishes the recursive relationship between temperature output at the current time step and measured power input at the previous time step.

Abstract: A device for rapidly instituting an active mode of a digital-television enabled system, the system including a first, volatile memory configured to load and store software instructions, includes: an input configured to receive first digital audio and video information; a first output configured to convey second audio and information toward a display regarding the first audio and video information; at least one second output configured to convey commands to, and receive information from, the first memory; and a processor configured to perform functions in accordance with software instructions stored in first and second memories and to cause the first memory to load software instructions for provision to the processor such that first instructions for processing at least one of the first audio information and the first video information are loaded and stored by the first memory with a higher priority than second instructions for performing other functionality.

Abstract: A page service request is received from a peripheral device requesting that a memory page be loaded into system memory. Page service request information corresponding to the received page service request is written as a queue entry into a queue structure in system memory. The processor is notified that the page request is present in the queue. The processor may be notified with an interrupt of a new queue entry. The processor processes the page service request and the peripheral device is notified of the completion of the processing of the request.

Abstract: Power gating control and related circuitry for integrated circuits is described herein. A centralized power gating control circuit uses trigger circuits to control the on/off switching of power gating circuits distributed at different points in a chip, integrated circuit, module or block (collectively “IC”). The power gating circuits may include power gates partitioned for sleep and shutdown modes. The shutdown mode power gates may employ multi-level power gate architecture to minimize inrush current during power-up of the IC. Each level may be associated with or tied to a trigger circuit and activated based on a voltage level reaching the voltage threshold of the trigger circuit. The power gating control and related circuitry may be embedded in the IC.

Abstract: A circuit design is simulated on a computing system. Simulating the circuit design includes selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design. A parity error is inserted in the first memory location during simulation of the design.

Abstract: A memory management unit is configured to receive requests for memory access from a plurality of I/O devices. The memory management unit implements a protection mode wherein the unit prevents memory accesses by the plurality of I/O devices by mapping memory access requests (from the I/O devices) to the same set of memory address translation data. When the memory management unit is not in the protected mode, the unit maps memory access requests from the plurality of I/O devices to different respective sets of memory address translation data. Thus, the memory management unit may protect memory from access by I/O devices using fewer address translation tables than are typically required (e.g., none).

Abstract: A system and a method of operating a chemical mechanical polishing (CMP) system comprises a slurry delivering unit configured for locally varying the supply of slurry while polishing the substrate. To this end, the slurry delivering unit may comprise at least one slurry outlet over a polishing pad of the CMP system, wherein the at least one slurry outlet is controllably movable to distribute slurry over the polishing pad.

Abstract: A sense amplifier for a SRAM device includes a PMOS differential pair and an NMOS differential pair to support operation with bit line precharge voltage as low as a few hundred millivolts without performance degradation, and generates a full rail output signal without any additional level shifter circuits. The PMOS differential amplifier includes tail current device coupled to a voltage higher than the bit line precharge voltage, and the NMOS differential amplifier includes tail current device coupled to a voltage lower than the bit line precharge voltage.

Abstract: A window position optimization for a pilot-aided OFDM system is disclosed. A method of reducing aliasing in an orthogonal frequency division multiplexing (OFDM) system, using window optimization and pilots comprises receiving an RF signal including a pilot, generating a channel frequency response estimate, interpolating the channel estimate to calculate a pilot carrier frequency response, and dynamically selecting a window to capture a channel impulse response to prevent aliasing.

Abstract: A method for performing channel estimation in an orthogonal frequency division multiplexing (OFDM) signal includes choosing reserved tones to be part of a pilot pattern, and using the reserved tones in the pilot pattern to perform the channel estimation. An apparatus for use in performing channel estimation in an OFDM system includes a receiver configured to receive a transmitted OFDM signal; a pilot symbol extractor configured to extract pilot symbols from the OFDM signal; and a channel estimator configured to perform the channel estimation, including using reserved tones as pilot tones.