Patents Assigned to Advanced Micro Devices
  • Patent number: 8589627
    Abstract: The present invention provides embodiments of a partially sectored cache. One embodiment of the apparatus includes a cache that includes a tag array for storing information indicating a plurality of tags and a data array for storing a plurality of lines. A first portion of the tags have a one-to-one association with a first portion of the lines and a second portion of the tags have a one-to-many association with a second portion of the lines.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Tarun Nakra
  • Patent number: 8585877
    Abstract: For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises controllably generating an actual value for at least one first process parameter by taking into account at least one previous value of the respective first process parameter, wherein each first process parameter is a process parameter of said at least two sets of process parameters.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roland Jaeger, Frank Wagenbreth, Frank Koschinsky
  • Patent number: 8587049
    Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: November 19, 2013
    Assignees: Spansion, LLC, Advanced Micro Devices, Inc.
    Inventors: Meng Ding, Amol Ramesh Joshi, Lei Xue, Takashi Orimoto, Kuo-Tung Chang
  • Patent number: 8589629
    Abstract: A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jonathan Owen, Guhan Krishnan, Carl D. Dietz, Douglas Richard Beard, William K. Lewchuk, Alexander Branover
  • Patent number: 8589661
    Abstract: A method and apparatus are presented for processing a stream of information, including preprocessing the stream, which includes partitioning the stream into packets of interest; determining boundaries for the packets of interest, wherein a packet boundary is either a start location or an end location for a packet; and making a record of the packet boundaries by setting a hint bit in a hint bit vector, a location of the hint bit within the hint bit vector corresponding to a position of the packet in the stream. The hint bit vector is split into two or more vectors, where the hint bits are assigned to one of the vectors on an alternating basis. The packets of interest are processed corresponding to the hint bits assigned to each vector in parallel over multiple clock cycles, wherein an original order of the packets of interest is maintained in the stream.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mike Butler, Donald A. Priore, Steven Beigelmacher
  • Patent number: 8586981
    Abstract: According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor test structure further includes at least two semiconductor body contacts situated on opposing sides of the doped halo, where one or more of the at least two semiconductor body contacts forms a direct electrical contact with the doped halo, thereby increasing current flow to the doped halo to facilitate measuring body-effect in the SOI transistor test structure.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Qiang Chen, Jung-Suk Goo
  • Patent number: 8587600
    Abstract: Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein the cache storage module is to initiate a storage of at least a portion of the compressed display data in the cache in response to an indication that the processing core is in an inactive mode. One method comprises, in response to an indication that a processor is in an inactive mode, transferring compressed display data from a frame buffer in memory to a cache associated with the processor, obtaining a first compressed display data from the cache, and decompressing the first compressed display data to generate a first uncompressed display data.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brett A. Tischler, Kenneth J. Kotlowski, Willard S. Briggs
  • Patent number: 8589670
    Abstract: A system provides a mechanism for increasing reliability by allowing margins to be evaluated and if one or more margins of a current configuration are too small, system configuration is modified to increase the margin. A computing device determines through training a first operating point of at least one operational characteristic of the system and a first margin associated therewith. The first margin is compared to a predetermined threshold margin and if the first margin is less than the predetermined threshold margin, the configuration of the system is adjusted to provide a configuration with greater margin for the operational characteristic. The system is retrained with the new configuration to determine a second operating point and a second margin associated therewith and compares the second margin to the threshold margin to determine if the second margin is more than the threshold margin, to satisfy reliability requirements.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ross V. La Fetra
  • Patent number: 8583971
    Abstract: A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: November 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sajosh Janarthanam, Jonathan Owen, Michael Osborn
  • Patent number: 8584065
    Abstract: A method and apparatus for designing an integrated circuit to operate at a desired clock frequency range reduces process variation by estimating the value of removable pessimism from a static timing analysis. The pessimism includes, for example, at least one of the removable on-chip-variation (OCV) margin from clock paths, removable OCV margin from data paths, removable IR drop margin from clock paths, and removable interconnects margin. At the timing analysis stage of a design flow, the method and apparatus determines the value of pessimism in the timing critical paths based on timing correlation between adjacent timing critical paths. In response to the determination, the value of pessimism may be reduced in the static timing analysis of the adjacent timing critical paths to optimize the timing performance of the integrated circuit at its desired clock frequency range.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: November 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arun Iyer, Yousuff Mohammed Shariff
  • Patent number: 8580660
    Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: November 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ming-Ren Lin, Judy Xilin An, Zoran Krivokapic, Cyrus E. Tabery, Haihong Wang, Bin Yu
  • Patent number: 8583894
    Abstract: A hybrid prefetch method and apparatus is disclosed. A processor includes a hybrid prefetch unit configured to generate addresses for accessing data from a system memory. The hybrid prefetch unit includes a first prediction unit configured to generate a first memory address according to a first prefetch algorithm and a second prediction unit configured to generate a second memory address according to a second prefetch algorithm. The hybrid prefetcher further includes an arbitration unit configured to select one of the first and second memory addresses and further configured to provide the selected one of the first and second memory addresses during a prefetch operation.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: November 12, 2013
    Assignee: Advanced Micro Devices
    Inventors: Swamy Punyamurtula, Bharath Narasimha Swamy
  • Patent number: 8584067
    Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: November 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael J. Osborn, Michael J. Tresidder, Aaron J. Grenat, Joseph Kidd, Priyank Parakh, Steven J. Kommrusch
  • Publication number: 20130297950
    Abstract: A method and system for determining voltage supplied to a processor from a voltage regulator when the voltage cannot be directly measured.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicant: Advanced Micro Devices, Inc.,
    Inventors: Michael J. Osborn, Sebastien Nussbaum, John P. Petry, Umair B. Cheema
  • Publication number: 20130298101
    Abstract: A method and apparatus generates thermal partitions for metal interconnects of an integrated circuit, based on interconnect self heat data and mutual heat data. Each of the thermal partitions includes data identifying thermally related interconnects and respective temperature values associated with each of the thermally related interconnects. Thermally related partitions that can be computed efficiently and simultaneously and the results then integrated using superposition for the full chips.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 7, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Rajit C. Chandra
  • Patent number: 8578129
    Abstract: In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: November 5, 2013
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Paul Blinzer, Leendert Peter Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Roy Woller, Arshad Rahman
  • Patent number: 8575029
    Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Moritz Andreas Meyer, Matthias Lehr, Eckhard Langer
  • Patent number: 8576236
    Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: November 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rodney C. Andre, Rex E. McCrary
  • Patent number: 8578141
    Abstract: A loop predictor and a method for instruction fetching using a loop predictor. A processor may include a loop predictor in addition to a primary branch predictor. A relatively common scenario in program execution is that a set of branches repeat over and over forming a loop. The loop may be detected based on a repeated pattern of access to a data structure used for branch prediction. Once a loop is detected and it may be determined whether the codes would stay in the loop for at least a duration sufficient to disable the branch prediction. On a determination that the detected loop is locked, a sequence of instruction addresses in one iteration of the detected loop may be captured in a buffer and the branch predictor may be turned off and a sequence of fetch instructions may be played from the buffer.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: November 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Anthony Jarvis
  • Patent number: 8573841
    Abstract: A method and apparatus for determining a temperature of a semiconductor device is provided herein. One aspect of the disclosed subject matter is seen in a temperature sensing device. The temperature sensing device comprises a diode and a circuit. The diode is adapted to be reverse biased by a charging voltage applied thereto. The circuit determines a temperature of the diode based on a rate that the voltage on the diode discharges in response to the charging voltage being uncoupled from the diode.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: November 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Golam R. Chowdhury, Arjang Hassibi