Abstract: Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the center of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate.

Abstract: An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the fins extend beyond the STI regions into the source and drain regions which are implanted within the semiconductor bulk. With bulk source and drain regions, reduced external FinFET resistance is provided, and with the fins extending into the bulk source and drain regions, improved thermal properties is provided over conventional silicon on insulator (SOI) devices.

Abstract: An apparatus is disclosed for performing cache prefetching from non-uniform memories. The apparatus includes a processor configured to access multiple system memories with different respective performance characteristics. Each memory stores a respective subset of system memory data. The apparatus includes caching logic configured to determine a portion of the system memory to prefetch into the data cache. The caching logic determines the portion to prefetch based on one or more of the respective performance characteristics of the system memory that stores the portion of data.

Abstract: A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.

Abstract: The present invention provides embodiments of an apparatus that includes a pad configurable for connection to a voltage source that provides a first voltage and a buffer connected to the pad. The buffer includes a plurality of transistors that have nominal breakdown voltages that are less than the first voltage. The buffer is configured to maintain voltage differentials on the plurality of transistors that are less than the break-down voltage of the plurality of transistors during pull-down of a pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage.

Abstract: A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Abstract: A method for displaying two different content items on a main display device and a remote device includes displaying content in a first display mode, generating a content switch event to switch from the first display mode to a second display mode, and displaying content in the second display mode. In the first display mode, a first content item is displayed on the main display device. In the second display mode, a second content item is displayed on the main display device, and the first content item is displayed on the remote device.

Abstract: Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.

Abstract: In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

Abstract: A bus protocol compatible requester includes a bus protocol port for transmitting bus protocol compatible requests to a bus protocol link, and an extended atomic operation generation system, coupled to the bus protocol port, for generating an extended atomic operation by using at least one bit in a field of a standard bus protocol request other than an opcode field, and providing the extended atomic operation to the bus protocol port for transmission to a completer. A bus protocol compatible completer includes a bus protocol port for receiving bus protocol compatible requests from a bus protocol link, and an extended atomic operation execution system, coupled to the bus protocol port, for decoding an extended atomic operation according to at least one bit in a field of a standard bus protocol request other than an opcode field, and executing the extended atomic operation according to the at least one bit.

Abstract: A method, apparatus and a system, for performing a process control using analysis of an upstream process is provided. The method comprises performing a first process on a workpiece and performing a qualitative analysis upon the workpiece relating to the first process, the qualitative analysis comprises analyzing at least one metrology measurement relating to the first process and a workpiece feature to evaluate a characteristic of the workpiece. The method further comprises selecting a process control parameter for performing a second process upon the workpiece based upon the qualitative analysis.

Abstract: A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.

Abstract: A contactless connector requires no physical contact. A terminated transmitting transmission line on a first board is parallel to a dual-terminated receiving transmission line on a second board. The boards are placed face-to-face with a small air gap in-between. A driver drives a driven pulse onto a first end of the transmitting transmission line. The driven pulse capacitively induces a positive induced pulse on the first end of the receiving transmission line. As the driven pulse travels from the first end to the second end of the transmitting transmission line, energy is transferred to the induced pulse, which travels down the receiving transmission line. Inductive coupling becomes stronger than capacitive as the length increases, so that at the second end, the induced pulse is negative and then swings positive. A Schmitt trigger receiver on the second end of the receiving transmission line detects the signal.

Abstract: A method and an apparatus are described that delay application of a higher order Power Density Multiplier (PDM) using a time based moving average of a number of active cores in a multicore system. A PDM is applied to a thermal design power budget of a thermal entity and performance of the thermal entity is increased by transferring available power from a thermal entity not in an active state to a thermal entity in an active state. Sufficient time is allowed for the cooling effect of reduced active cores, to influence the active core that receives the extra power (a higher PDM). Similarly delaying application of a lower PDM with the same moving average, but a different threshold, allows a core to retain a higher power allocation until the more active neighbor core(s) cause it to heat up, thereby boosting core performance.

Abstract: The loop bandwidth of a PLL is adjusted based on a difference between the output signal of the PLL and the PLL reference signal. In an embodiment, the DC open loop gain and natural frequency of the PLL are adjusted based on the phase difference between the output signal and the reference signal, so that the loop bandwidth of the PLL is increased when the phase difference is outside a programmable range and is decreased when the phase difference is within the programmable range.

Abstract: In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

Abstract: A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.

Abstract: A data processing device includes one or more state registers to store state information associated with an execution core of the device. Each state register includes an associated “dirty” bit. When a guest program is executed at the execution core, a dirty bit is set in response to a change in the state information at the associated state register. In response to a world switch from the guest program to a VMM, the state information at each state register is stored to memory only if the associated dirty bit is set. In addition, if the VMM changes any stored state information, it clears a “clean” bit associated with the changed information. In response to a world switch from the VMM to a guest, the state information associated with cleared clean bits is retrieved from memory.

Abstract: A method for enhanced forward rendering is disclosed which includes a depth pre-pass, light culling and a final shading. The depth pre-pass minimizes the cost of final shading by avoiding high pixel overdraw. The light culling stage calculates a list of light indices overlapping a pixel. The light indices are calculated on a per-tile basis, where the screen has been split into units of tiles. The final shading evaluates materials using information stored for each light. The forward rendering method may be executed on a processor, such as a single graphics processing unit (GPU) for example.