Abstract: A WLAN (Wireless Local Area Network) receiver having a synchronization unit is provided. The synchronization unit comprises a first functional unit for performing a first signal processing function, a second functional unit for performing a second signal processing function different from the first signal processing function, and at least one signal processing circuit. In the synchronization unit the first functional unit is operating at least one of the signal processing circuits for performing the first signal processing function, and the second functional unit is arranged for operating the at least one signal processing circuit operated by the first functional unit for performing the second signal processing function. Since the above-described signal processing circuits or modules can be re-used for the antenna diversity unit and the preamble detection unit this results in a smaller number of gates and an improved density of the circuitry.

Abstract: Controlling access to a control register of a microprocessor. A method of controlling access to a control register such as CR3, for example, of a processor having a normal execution mode and a secure execution mode may include storing address translation table information in the control register, allowing a software invoked write access to modify the address translation table information during the normal execution mode and selectively inhibiting the software invoked write during the secure execution mode.

Abstract: A method of controlling a secure execution mode-capable processor includes allowing a plurality of interrupts to interrupt the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a non-secure execution mode. The method also includes disabling the plurality of interrupts from interrupting the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a secure execution mode.

Abstract: In one example, the method includes operating a process tool that has a plurality of sensors for sensing at least one parameter associated with the operation of the process tool, obtaining data from the sensors and determining at least one maintenance activity for the process tool based upon the data obtained from the sensors. In another example, data from the sensors is provided to a controller that analyzes the data and indicates desired variations in at least one maintenance activity to be performed on the process tool based upon the analysis of the data. In yet another example, the controller identifies a plurality of maintenance activities to be performed on the process tool based upon the analysis of the data.

Abstract: A diagnosis mechanism for host controllers such as USB (Universal Serial Bus) host controllers is provided. The host controller has a register set that comprises at least one host controller capability register storing data indicative of operational capabilities of the host controller, and at least one host controller operational register storing data for controlling the operation of the host controller. The at least one host controller capability register stores data that is indicative of available diagnostic modes that the host controller can enter. The at least one host controller operational register stores diagnosis data for controlling the operation of the USB host controller in diagnostic modes. This diagnosis mechanism may improve the reliability of the host controller operation.

Abstract: In a production line, a cluster tool having a plurality of substantially identical process modules and a metrology tool includes a control unit that allows one to receive, store and process information that indicates in which process module which substrates have been processed and which selects, on the basis of the process information, which substrate has to be subjected to a measurement. Advantageously, the substrates are selected so that each process module is represented by a corresponding substrate to be measured in order to reliably monitor the process quality of each process module.

Abstract: A wireless local area network receiver is provided that has an interference reduction unit for reducing interchip interference in a received signal that is modulated using a complementary code keying technique such as CCK-11. The interference reduction unit comprises a decision feedback equalizer that has a feedforward filter for reducing precursor interference and a feedback filter for reducing postcursor interference in the received signal. The receiver may perform channel estimation to optimize the filter coefficients during the preambles of the incoming sequence.

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Abstract: A memory controller includes a power mode sensitive reordering device coupled to receive a power mode indication. The memory controller includes a selectable high and low power mode. An indication of which of the high and low power modes is selected is coupled to the power mode sensitive reordering device as the power mode indication. In the low power mode, memory transactions are reordered to minimize power consumption in memory devices controlled by the memory controller.

Abstract: A wireless local area network transceiver, an integrated circuit chip, a PLL (Phase Locked Loop) device and a method are provided that may reduce influences of switching noise. The frequency of an output signal of the PLL device is divided in a prescaler of the PLL device by a prescaler factor. The prescaler is operable in at least two modes with each mode having assigned a different prescaler factor. An accumulator is implemented in the PLL circuit for generating a mode switching signal for changing the mode of the prescaler. The generation of the mode switching signal is done by storing an accumulator value and processing a modulus function for updating the accumulator value. The provided technique may allow for reducing disturbances caused by switching the mode of the prescaler in the PLL circuit.

Abstract: A method and system of controlling a process from run-to-run for semiconductor manufacturing. The method of control utilizes a process model to establish a relationship between process control input data and process control output data. The method of control involves minimizing the difference between target process control output data and process control output data predicted by applying the process model to the new process control input data.

Abstract: A method for managing recipes in a semiconductor manufacturing process which includes resolving a recipe to provide a resolved recipe using a configuration for a current context and rendering the recipe to provide a rendered recipe. The rendered recipe corresponds to a format suitable for consumption by an equipment interface of the semiconductor manufacturing process.

Abstract: Patch servers, patch clients and corresponding methods are provided that may increase secret protection and key loss tolerance. A patch server includes a first key generation platform and a second key generation platform different from the first one. A first and second private key group containing a plurality of first or second private keys, respectively, is generated using the first or second key generation platform, respectively. One of the first private keys is selected from the first private key group, and one of the second private keys is selected from the second private key group. A first digital signature is generated based on the patch and the first selected private key. A second digital signature is generated based on the patch and the second selected private key. The patch is transmitted to the patch client together with the first and second digital signatures.

Abstract: A method of making a device using a lithographic system having a lens from which an exposure pattern is emitted. A conforming immersion medium can be positioned between a photo resist layer and the lens. The photo resist layer, which can be disposed over a wafer, and the lens can be brought into intimate contact with the conforming immersion medium. The photo resist can then be exposed with the exposure pattern so that the exposure pattern traverses the conforming immersion medium.

Abstract: A method for generating a cost function includes providing a resource for processing a workpiece. A plurality of cost function parameters is provided. A library of parameterized cost function components is acessed based on the plurality of cost function parameters to generate a cost function for processing the workpiece using the resource. A system includes a resource for processing a workpiece and at least one scheduling agent. The scheduling agent is configured to provide a plurality of cost function parameters and access a library of parameterized cost function components based on the plurality of cost function parameters to generate a cost function for processing the workpiece using the resource.

Abstract: A task queue management technique leverages infrastructure provided by file and operating systems to manage task queues substantially without otherwise typical problems regarding management of the size of the queue and/or the state of the queue (e.g., empty or full) while maintaining, regulating and altering the queue and the order of tasks in the queue. Task producer code is configurable to cause one or more executable files corresponding to each of one or more tasks to be stored in a queue directory responsive to receiving the one or more tasks. A file system associates each executable file with a time stamp indicating when the executable file was stored. Task consumer code is configurable to execute the one or more executable files in an order indicated by the time stamps associated with the executable files and to remove each executable file after execution of each executable file.

Abstract: For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.

Abstract: A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a plurality of storage blocks, each configured to store a plurality of data units. Each of the plurality of storage blocks may be accessed asynchronously. In addition, the cache subsystem includes a plurality of tag units which are coupled to the plurality of storage blocks. Each of the tag units may be configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within the plurality of storage blocks. Each of the plurality of tag units may be accessed synchronously.

Abstract: By maintaining the gate electrode covered during the process flow for forming metal silicide regions in the drain and source of a field effect transistor, an appropriate metal silicide may be formed on the gate electrode which meets the requirement for aggressive gate length scaling. Preferably, a nickel silicide is formed on the gate electrode, whereas the drain and source regions receive the well-established cobalt disilicide. Additionally, the gate electrode dopant profile is effectively decoupled from the drain and source dopant profile.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of the buried insulation layer, the oxide trap region having a plurality of oxide traps to promote carrier recombination.