Abstract: It has been discovered that system operational characteristics (e.g., power level, clock frequency, processor utilization, operating system time slice utilization, size and age of queued jobs) may be used to predict storage access requirements for the system. By predicting the storage access requirements of a system, a storage subsystem may be advantageously controlled to anticipate storage accesses. A storage device or array of such devices can be configured to operate, for example, at selected speeds no greater than that required to process the predicted storage access requirements. The storage access prediction may be based, for example, on the frequency and voltage at which a processor is running or based on other system performance indicators such as job backlog and age and size thereof. Various controllable characteristics such as the speed of a hard drive's storage media, the current applied to a read/write head, etc.

Abstract: A method for fabricating a body-tied SOI transistor with reduced body resistance is presented. During the wafer fabrication process, a semiconductor wafer is placed in an ion implantation device and oriented to a first position relative to a beam path of the ion implantation device in order to obtain a substantially non-orthogonal twist orientation between the beam path and the transistor gate edge. Following this orientation of the first position, an ion species is implanted into a first implantation region. The wafer is then rotated to a second substantially non-orthogonal twist orientation, where another ion implantation is conducted. This process continues in the same manner, such that further substantially non-orthogonal twists and ion implantations are conducted, until the desired number of implantation areas is created. Halo or pocket implants are an example of the type of implantations to which the technique may be applied.

Abstract: An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.

Abstract: By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.

Abstract: A system includes a memory operable to store scrambled data at a plurality of memory locations. The system also includes an empty detector operable to determine whether a specified memory location is empty using contents of the specified memory location. The contents of the specified memory location are not descrambled for use by the empty detector in determining whether the specified memory location is empty.

Abstract: A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.

Abstract: A method for failure analysis of small contacts in integrated circuits is provided. A number of opposing electrical contacts is configured to contact a sample in an offset pattern such that any one electrical contact may contact more than one conductor in the sample and any opposing electrical contact is offset-positioned to contact no more than one of the conductors contacted by the one electrical contact.

Abstract: Methods of making a semiconductor structure are disclosed. A refractory metal layer containing W, TiW, Ta, or TaN and semiconductor layer are formed on a substrate that contains copper in, for example, a via therein. A portion of the refractory metal layer and semiconductor layer is removed by etching using a fluorine-containing compound. By using W, TiW, Ta, or TaN as the refractory metal layer material and employing fluorine-based etching, the copper portion in the substrate is not substantially etched, thus preventing corrosion of the copper portion.

Abstract: An integrated device includes a voltage mode transmit driver for matching an output impedance to an output transmission line based on a binary code, an input termination module configured for matching an input impedance to an input transmission line based on an input impedance calibration value using thermometer-based decoding. The voltage mode transmit driver includes, for each differential output signal, a resistor network circuit having pull-up circuits and pull-down circuits for changing the voltage on the differential output signal, and having binary weighted resistance values relative to each other. The input termination module includes pull-up circuits and pull-down circuits having inverse hyperbolic resistance values relative to each other, and using thermometer-based decoding to ensure a linear change in input impedance during transitions in the input impedance calibration value.

Abstract: A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source drain region. A first epitaxial layer is formed overlying the second source drain prior to removal of the first protective layer.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

Abstract: A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache for storage in one of the plurality of trace cache entries. The trace generator may be configured to detect an exceptional instruction within the group of instructions and to prevent the exceptional instruction from being stored in a same one of the plurality of trace cache entries as any non-exceptional instruction.

Abstract: A method and system for maintaining synchronization in a home network is disclosed. The home network includes a host ethernet media access controller and an HPNA chip, where control frame and data frame pairs are transferred between the host ethernet media access controller (MAC) and the HPNA chip. The method and system include sending a null frame from the host ethernet MAC to the HPNA chip prior to the data frame, and recognizing the null frame on the HPNA chip as an indication that a next received frame will be the data frame, thereby maintaining synchronization between the control frame and the data frame pairs.

Abstract: A memory controller may be implemented using dynamic page conflict prediction to control the closure of memory pages. A memory controller may include a page history register configured to store a value indicating the pattern of page conflicts encountered by a memory device. The memory controller may include a global conflict predictor for storing probabilities of page conflicts associated with values of the page history register. In response to receiving a memory access request, a control unit may be configured to determine whether the memory access request causes a page conflict. The memory controller may be configured to update the global conflict predictor based on this determination. If a page conflict is predicted, the memory controller may automatically close the targeted page (e.g., by initiating the memory access in auto-precharge mode) upon completion of the memory access requested by the memory access request.

Abstract: A structure, for testing relative to an MOS transistor, closely resembles the MOS transistor of interest. For example, certain dimensions and a number of dopant concentrations typically are substantially the same in the test structure as found in corresponding elements of the MOS transistor of interest. However, the regions of the test structure corresponding to the source and drain of the transistor have no halos or extensions that might cause gate overlap; and in the test structure, these regions are of a semiconductor type opposite the type found in the source and drain of the transistor. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for direct electrical measurement of gate length.

Abstract: A cache memory system including a cache memory employing a tag including associated touch bits. The system includes a first cache memory subsystem having a first cache storage and a second cache memory subsystem including a second cache storage. The first cache storage may store a first plurality of cache lines of data. The second cache storage may store a second plurality of cache lines of data. Further the second cache memory subsystem includes a tag storage which may store a plurality of tags each corresponding to a respective cache line of the second plurality of cache lines. In addition, each of said plurality of tags includes an associated bit indicative of whether a copy of the corresponding respective cache line is stored within the first cache memory subsystem.

Abstract: A method of forming an interlevel dielectric (ILD) layer forms a polymer sacrificial ILD on a substrate. After metallization structures are formed in the polymer sacrificial ILD layer, a low power etch back is performed on the sacrificial ILD layer. Dielectric material is non-conformally deposited as an ILD layer over the substrate and the metallization structures, forming air gaps between some of the metallization structures.

Abstract: Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments further include dual damascene (100A, 100B) processing using Cu metallization (100).

Abstract: In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate in an area above the doped region and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors.

Abstract: A method and apparatus for loop detection for improved branch prediction accuracy. In one embodiment, the method may comprise executing a branch instruction, updating a plurality of event counts corresponding to the branch instruction in response to its executing, determining a loop behavior status corresponding to the branch instruction in response to the event count updating, and promoting the branch instruction to a loop branch prediction type in response to the determination of loop behavior status.