Abstract: A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.

Abstract: Semiconductors having electrically coupled gate and impurity doped regions and methods for fabricating the same are provided. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and an impurity doped region within the substrate. A first spacer is formed on a first side and a second spacer on a second side of the gate electrode. An ion is implanted into the first spacer with an angle greater than zero from an axis perpendicular to the surface of the substrate. The first spacer is etched to remove a portion thereof and a silicon film is deposited overlying a remainder of the first spacer, the impurity doped region and the second spacer. The silicon film is etched, forming a silicon spacer, and a silicide-forming metal is deposited to form a silicide contact that electrically couples the gate electrode and the impurity doped region.

Abstract: An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

Abstract: An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

Abstract: In a method of forming a semiconductor structure, a substrate comprising at least one contact pad is provided. A passivation layer is formed over the substrate. A mask which does not cover a portion of the passivation layer located over the at least one contact pad is formed over the passivation layer. An etching process adapted to remove a material of the passivation layer is performed and the mask is removed. Then, a second etching process adapted to remove residues of the passivation layer from the contact pad can be performed. The removal of the mask may be performed at a temperature of the substrate in a range from about ?20° C. to about 100° C. The second etching process can comprise exposing the substrate to a gaseous etchant comprising hydrogen and fluorine, an amount of hydrogen in the etchant being about equal to an amount of fluorine, or greater. Thus, a formation of oxides and/or fluorides on the at least one contact pad can be avoided.

Abstract: A WLAN (Wireless Local Area Network) receiver with a synchronization unit is provided, wherein the synchronization unit comprises a frequency error correction unit configured to perform a frequency error correction process, a phase error correction unit configured to perform a phase error correction process, a filter circuit capable of applying one of at least two different filter transfer functions, wherein a first one of said at least two different filter transfer functions is a frequency error correction filter transfer function for use in said frequency error correction process and a second one of said at least two different filter transfer functions is a phase error correction filter transfer function for use in said phase error correction process, and a controller unit connected to said filter circuit to select one of said at least two different filter transfer functions.

Abstract: An improved compression and decompression technique to maximize the utilization of low capacity data storage while minimizing the decompression time. In one embodiment, software files comprising a file header and a plurality of records are compressed to generate a compressed file header and a single record that contains a compressed image of the original plurality of records. Upon execution, the record is decompressed and portions of the compressed images corresponding to destination addresses are decompressed to allow a decompressor to directly place the decompressed records in the desired destination. In another embodiment of the invention, software files comprising a file header and a plurality of records are individually compressed to generate a compressed file header and a plurality of compressed records.

Abstract: The present invention provides a method for supporting frame priority in a home phone line network. The method includes: detecting a limited automatic repeat request (LARQ) header in a frame with a priority tag; stripping the LARQ header and a frame check sequence (FCS) in the frame with the priority tag; recalculating the FCS for the stripped frame with the priority tag; and adding the recalculated FCS to the stripped frame with the priority tag. The method strips the LARQ header from a HPNA frame with the priority tag before it is sent to an Ethernet controller. By stripping the LARQ header, the Ethernet controller will correctly recognize the priority tag and send the frame to the appropriate priority queue. In this manner, frame priority is supported.

Abstract: In response to a cold reset in a computer system, a plurality of indications in a nonvolatile memory are initialized to a first state. Each of the plurality of indications is assigned to a respective one of a plurality of tasks to be executed on one or more processors of the computer system. A first task of the plurality of tasks is executed, including changing a first indication of the plurality of indications to a second state, wherein the first indication is assigned to the first task. A computer accessible medium comprising one or more instructions implementing the initialization and one or more instructions comprise the first task is also contemplated, as well as a computer system including a processor and the computer accessible medium.

Abstract: A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.

Abstract: A storage device host controller such as an SATA (Serial ATA) host controller and a corresponding method are provided for performing host-to-device and device-to-host communications in a PIO (Programmed I/O) data transfer mode and a DMA (Direct Memory Access) data transfer mode. The host controller comprises a buffer unit for buffering data and a data stream selection unit for selecting a data stream for submission to the buffer unit. The data stream selection unit is connected to receive at any one time at least one of a host-to-device data stream in the PIO data transfer mode, a host-to-device data stream in the DMA data transfer mode, a device-to-host data stream in the PIO data transfer mode, and a device-to-host data stream in the DMA data transfer mode, and select from the received data streams the data stream to be submitted to the buffer unit.

Abstract: In one embodiment, a processing node includes a plurality of processor cores and a reconfigurable interconnect. The processing node also includes a controller configured to schedule transactions received from each processor core. The interconnect may be coupled to convey between a first processor core and the controller, transactions that each include a first corresponding indicator that indicates the source of the transaction. The interconnect may also be coupled to convey transactions between a second processor core and the controller, transactions that each include a second corresponding indicator that indicates the source of the transaction. When operating in a first mode, the interconnect is configurable to cause the first indicator to indicate that the corresponding transactions were conveyed from the second processor core and to cause the second indicator to indicate that the corresponding transactions were conveyed from the first processor core.

Abstract: A method is provided for controlling interrupts in a secure execution mode-capable processor. The method includes detecting an interrupt and performing a predetermined routine in response to detecting the interrupt. The method further includes performing a second routine prior to performing the predetermined routine in response to detecting the interrupt depending upon whether the processor is operating in a secure execution mode.

Abstract: A semiconductor component having a tuned variable resistance resistor and a method for manufacturing the tuned variable resistance resistor. A semiconductor process for manufacturing a semiconductor component is selected. For the selected process, the tuned variable resistance resistor is characterized to determine the maximum stress current as a function of the width of the tuned variable resistance resistor. Then, for a given width and maximum stress current, the voltages across the resistors are characterized as a function of length. A tuned variable resistance resistor having a length and width capable of sustaining a predetermined maximum stress current is integrated into a semiconductor component. The semiconductor component may include protection circuitry designed in accordance with the Human Body Model, the Charge Device Model, or both.

Abstract: The present invention is generally directed to various methods of controlling properties and characteristics of a gate insulation layer based upon electrical test data, and a system for performing same. In one illustrative embodiment, the method comprises performing at least one electrical test on at least one semiconductor device, determining at least one parameter of at least one process operation to be performed to form at least one gate insulation layer on a subsequently formed semiconductor device based upon electrical data obtained from the electrical test, and performing at least one process operation comprised of the determined parameter to form the gate insulation layer.

Abstract: A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may be configured to query the bus for peripheral devices by reading each address on the bus. During the querying process, the host controller may detect one or more peripheral devices coupled to the bus. Following the completion of the querying of the bus, the host controller may then begin reading configuration information from each of the detected devices. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device.

Abstract: The physical movement of reticles and solder bump masks within a wafer processing plant are continually tracked and documented in a historical database for the useful life of the reticles or masks. In an example embodiment of the mask tracking method, the method includes moving the masks from one location to another in mask pods. In addition, a mask data set is generated for each mask composed of a mask identification code cross-referenced to a pod identification code and the mask data sets are processed by a computer arrangement. The mask data sets are then updated in the computer arrangement to include a facility location identification code as each mask moves to a subsequent location during wafer processing. The present invention provides the advantage that wafer lots and reticles can be matched to an event on the processing line and stored as data for later review and analysis.

Abstract: In a personal Internet communication device, a security key is stored on the master boot record. Any bootable device attempting to write operating system files or software files must have an authorized signature key in order to be eligible to install files on the personal Internet communication device.

Abstract: A signal pre-processing device particularly in wireless LAN devices is provided that comprises an AGC (Automatic Gain Control) unit, an ADC (Analog-to-Digital Converting) unit and a normalization unit. The AGC unit amplifies a received analog input signal and outputs an amplified analog signal. Further, it automatically controls an amplification gain when amplifying the analog input signal. The ADC unit receives the amplified analog signal, converts it into a digital signal and outputs the digital signal. The normalization unit is receives the digital signal, applies a normalization function to the digital signal and outputs the normalized digital signal. Thus, less precise AGC units can be used, thereby reducing production costs as well as the size and complexity of the AGC unit. Further, shorter circuit development times are obtainable.

Abstract: Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.