Patents Assigned to Advanced Micro Devics, Inc.
-
Patent number: 11790593Abstract: A technique for performing a ray tracing operation for a ray is provided. The method includes performing one or more ray-box intersection tests for the ray against one or more bounding boxes of a bounding volume hierarchy to eliminate one or more nodes of the bounding volume hierarchy from consideration, for one or more triangles of the bounding volume hierarchy that are not eliminated by the one or more ray-box intersection tests, performing one or more ray-triangle intersection tests utilizing samples displaced from a centroid position of the ray, and invoking one or more shaders of a ray tracing pipeline for the samples based on results of the ray-triangle intersection tests.Type: GrantFiled: March 13, 2020Date of Patent: October 17, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Chen Huang
-
Patent number: 11789655Abstract: A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response performs at least one pre-work action that reduces a latency of the decoded memory command of the second type.Type: GrantFiled: September 30, 2021Date of Patent: October 17, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Guanhao Shen, Ravindra Nath Bhargava
-
Patent number: 11790435Abstract: Systems, methods and apparatuses are disclosed for implementation and management of a dynamic compute and application marketplace. The dynamic computer marketplace system can coordinate access to one or more other computing resources, including on-premises computing resources, external (or off-premises) computing resources or a combination thereof. In various embodiments, the dynamic computer marketplace system advantageously can be used to facilitate inter-provider migration, transparent pricing, and/or competitive pricing, among other things.Type: GrantFiled: April 23, 2021Date of Patent: October 17, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Jesse Barnes, Max Alt
-
Patent number: 11790590Abstract: Techniques for executing computing work by a plurality of chiplets are provided. The techniques include assigning workgroups of a kernel dispatch packet to the chiplets; by each chiplet, executing the workgroups assigned to that chiplet; for each chiplet, upon completion of all workgroups assigned to that chiplet for the kernel dispatch packet, notifying the other chiplets of such completion; and upon completion of all workgroups of the kernel dispatch packet, notifying a client of such completion and proceeding to a subsequent kernel dispatch packet.Type: GrantFiled: March 31, 2021Date of Patent: October 17, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Milind N. Nemlekar, Maxim V. Kazakov, Prerit Dak
-
Patent number: 11791008Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.Type: GrantFiled: January 24, 2022Date of Patent: October 17, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Glennis Eliagh Covington, Benjamin Lyle Winston, Santha Kumar Parameswaran, Shannon T. Kesner
-
Patent number: 11789620Abstract: A phase training update circuit operates during a self-refresh cycle of a memory to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.Type: GrantFiled: December 23, 2021Date of Patent: October 17, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Scott P. Murphy, Huuhau M. Do
-
Patent number: 11789734Abstract: A computing system includes a processing unit and a memory storing instructions that, when executed by the processor, cause the processor to receive program source code in a compiler, identify in the program source code a set of operations for vectorizing, where each operation in the set of operations specifies a set of one or more operands, in response to identifying the set of operations, vectorize the set of operations by, based on the number of operations in the set of operations and a total number of lanes in a first vector register, generating a mask indicating a first unmasked lane and a first masked lane in the first vector register, based on the mask, generating a set of one or more instructions for loading into the first unmasked lane a first operand of a first operation of the set of operations, and loading the first operand into the first masked lane.Type: GrantFiled: August 9, 2019Date of Patent: October 17, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Anupama Rajesh Rasale
-
Publication number: 20230325313Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.Type: ApplicationFiled: April 17, 2023Publication date: October 12, 2023Applicant: Advanced Micro Devices, Inc.Inventor: Paul J. Moyer
-
Publication number: 20230325326Abstract: A memory controller includes encryption circuits for encrypting write data to be written to an address in a RAM memory. A tweak value is provided based at least on the address. The tweak value is encrypted with Advanced Encryption Standard (AES) encryption using a first key. A first block write data is encrypted by manipulating it based on the encrypted tweak value, AES encrypting with a second key, and then manipulating the result based on the encrypted tweak value again. For subsequent blocks of write data, the encrypted tweak value is modified, and a similar operation is performed.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Applicant: Advanced Micro Devices, Inc.Inventor: Kedarnath Balakrishnan
-
Publication number: 20230324967Abstract: Package lids with carveouts configured to expose lights directly connected to an internal component of a processor are described. Lid carveouts are configured to precisely align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device via a press fit connection, while maintaining visibility of lights directly connected to processor internal components when the cooling device is connected. Lid carveouts are further configured to expose one or more connectors disposed on a processor surface that supports its internal component. When contacted by corresponding connectors of an auxiliary device, such as a light not integrated into a processor package or a cooling device, the lid carveouts enable direct connections between the package’s internal components and the auxiliary device.Type: ApplicationFiled: March 25, 2022Publication date: October 12, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Amitabh Mehra, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
-
Publication number: 20230324947Abstract: User configurable hardware settings for overclocking is described. In accordance with the described techniques, user input to adjust hardware settings for operating a processing unit in an overclocking mode is received. The user input, for example, adjusts at least one of a voltage droop threshold or a frequency adjustment of the clock rate. A voltage droop is detected while operating the processing unit in the overclocking mode. Responsive to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware settings.Type: ApplicationFiled: March 25, 2022Publication date: October 12, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Amitabh Mehra, William Robert Alverson, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
-
Patent number: 11782848Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.Type: GrantFiled: September 14, 2020Date of Patent: October 10, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Amit P. Apte, Ganesh Balakrishnan, Vydhyanathan Kalyanasundharam, Kevin M. Lepak
-
Patent number: 11782640Abstract: A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response elevates at least one of the priority and the age of a decoded command of the first type that accesses the first memory region already stored in the command queue.Type: GrantFiled: March 31, 2021Date of Patent: October 10, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Guanhao Shen, Ravindra Nath Bhargava
-
Patent number: 11782897Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of at least one bit in a lookup address at least once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.Type: GrantFiled: April 15, 2022Date of Patent: October 10, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Steven R. Havlir, Patrick J. Shyvers
-
Patent number: 11782838Abstract: Techniques for prefetching are provided. The techniques include receiving a first prefetch command; in response to determining that a history buffer indicates that first information associated with the first prefetch command has not already been prefetched, prefetching the first information into a memory; receiving a second prefetch command; and in response to determining that the history buffer indicates that second information associated with the second prefetch command has already been prefetched, avoiding prefetching the second information into the memory.Type: GrantFiled: March 31, 2021Date of Patent: October 10, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Anirudh R. Acharya, Alexander Fuad Ashkar
-
Patent number: 11783529Abstract: A technique for performing ray tracing operations is provided. The technique includes combining one or more common exponent values of a compressed box node with one or more minimum vertex mantissas of the compressed box node and one or more maximum vertex mantissas of the compressed box node to obtain one or more minimum vertices and one or more maximum vertices; and combining a minimum vertex of the one or more minimum vertices and a maximum vertex of the one or more maximum vertices to obtain a bounding box for a compressed box data item of the compressed box node.Type: GrantFiled: December 27, 2021Date of Patent: October 10, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Chen Huang
-
Publication number: 20230315188Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Thomas J. Gibney, Mihir Shaileshbhai Doctor, Indrani Paul, Benjamin Tsien, Stephen V. Kosonocky, John P. Petry, Christopher T. Weaver
-
Publication number: 20230315657Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Bryan Broussard, Pravesh Gupta, Benjamin Tsien, Vydhyanathan Kalyanasundharam
-
Publication number: 20230315320Abstract: A page swapping memory protection system tracks accesses to physical memory pages, such as in a table with each row storing a physical memory page address and a counter value. This counter value records the number of accesses (e.g., read access or write accesses) to the corresponding physical memory page. In response to one of the counters exceeding a threshold value, the corresponding physical memory page is swapped with another page in physical memory (e.g., a page the table indicates has a smallest number of accesses). According, unreliability in the physical memory introduced due to frequent accesses to a particular physical memory page is mitigated.Type: ApplicationFiled: March 24, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: SeyedMohammad SeyedzadehDelcheh, Sriseshan Srikanth
-
Publication number: 20230315171Abstract: Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.Type: ApplicationFiled: March 25, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Amitabh Mehra, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
