Abstract: A method of manufacturing a semiconductor package structure is provided. The method includes providing a first carrier, forming a patterned buffer layer over the first carrier, forming a first redistribution structure that includes forming a first dielectric layer on the patterned buffer layer, after an electrical testing by applying an electric signal towards the first redistribution structure, removing the first carrier, removing portions of the first dielectric layer, resulting in a patterned first dielectric layer, the patterned first dielectric layer exposing portions of the first circuit layer, removing the exposed portions of the first circuit layer, using the patterned first dielectric layer as a mask, resulting in a patterned first circuit layer, and forming an electric conductor in a recess defined by the patterned first dielectric layer and the patterned first circuit layer.

Abstract: A semiconductor device package includes a redistribution layer, a first semiconductor device, a first connection structure, and a first conductive layer. The first semiconductor device can be disposed on the redistribution layer. The first connection structure can be disposed between the first semiconductor device and the redistribution layer. The first conductive layer can surround the first connection structure.

Abstract: An electronic device package includes a first conductive substrate, a second conductive substrate and a dielectric layer. The first conductive substrate has a first coefficient of thermal expansion (CTE). The second conductive substrate is disposed on an upper surface of the first conductive substrate and electrically connected to the first conductive substrate. The second conductive substrate has a second CTE. The dielectric layer is disposed on the upper surface of the first conductive substrate and disposed on at least one sidewall of the second conductive substrate. The dielectric layer has a third CTE. A difference between the first CTE and the second CTE is larger than a difference between the first CTE and the third CTE.

Abstract: A sensing module, a semiconductor device package and a method of manufacturing the same are provided. The sensing module includes a sensing device, a first protection film and a second protection film. The sensing device has an active surface and a sensing region disposed adjacent to the active surface of the sensing device. The first protection film is disposed on the active surface of the sensing device and fully covers the sensing region. The second protection film is in contact with the first protection film and the active surface of the sensing device.

Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.

Abstract: A semiconductor device package includes a semiconductor device in an encapsulating layer, an electrical conductor for electrical connection of the semiconductor device to an external device, and a redistribution structure for electrical connection between the semiconductor device and the electrical conductor. The redistribution structure includes dielectric layers stacked on each other in a direction extending between the encapsulating layer and the electrical conductor, wherein the dielectric layer most adjacent to the electrical conductor includes a first pattern under the electrical conductor, and circuit layers each corresponding to a respective one of the dielectric layers.

Abstract: A semiconductor assembly includes a first wiring structure, a first semiconductor die and a first electronic element. The first wiring structure has a first surface. The first semiconductor die is disposed on the first surface of the first wiring structure. The first electronic element is electrically connected to the first wiring structure. The first electronic element includes a first metal layer, a second metal layer and a dielectric material interposed between the first metal layer and the second metal layer. The first metal layer and the second metal layer are substantially perpendicular to the first surface of the first wiring structure.

Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

Abstract: A semiconductor device includes a dielectric layer, a first conductive layer penetrating the dielectric layer, and a grounding structure disposed within the dielectric layer and adjacent to the first conductive layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first conductive layer has a first portion and a second portion connected to the first portion. The first portion has a width greater than that of the second portion.

Abstract: A device structure includes a stacked structure, a dielectric material, and an electrode via. The stacked structure includes a first metal oxide layer, a second metal oxide layer and a metal layer. The second metal oxide layer is opposite to the first metal oxide layer. The metal layer is interposed between the first metal oxide layer and the second metal oxide layer. The dielectric material extends through the first metal oxide layer. The electrode via extends through the dielectric material and electrically connected to the metal layer.

Abstract: An inductor structure includes a carrier, a coil structure, an isolation structure and a ferromagnetism structure. The carrier has an upper surface. The coil structure is disposed adjacent to the upper surface of the carrier. The isolation structure covers the upper surface and the coil structure. The ferromagnetism structure is disposed on the isolation structure.

Abstract: A thermal conduction unit includes a conductive via, a periphery conductor and an isolation material. The conductive via includes a first thermoelectric material. The periphery conductor encloses the conductive via and includes a second thermoelectric material. An end of the periphery conductor is electrically connected to an end of the conductive via. The isolation material is interposed between the conductive via and the periphery conductor.

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

Abstract: A semiconductor device package includes a carrier, a patterned passivation layer and a first patterned conductive layer. The patterned passivation layer is disposed on the carrier. The first patterned conductive layer is disposed on the carrier and surrounded by the patterned passivation layer. The first patterned conductive layer has a first portion and a second portion electrically disconnected from the first portion. The first portion has a first surface adjacent to the carrier and exposed by the patterned passivation layer. The second portion has a first surface adjacent to the carrier exposed by the patterned passivation layer. The first surface of the first portion is in direct contact with an insulation medium.

Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.

Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.

Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.

Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The semiconductor substrate includes a dielectric layer, at least one first conductive trace, and a conductive via. The dielectric layer has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive trace is disposed adjacent to the first dielectric surface of the dielectric layer. The conductive via is disposed adjacent to the second dielectric surface of the dielectric layer and connected to the first conductive trace, where the conductive via and the first conductive trace are connected at a first interface leveled with about a half thickness of the dielectric layer.

Abstract: A semiconductor device package includes a dielectric layer and a stacking conductive structure. The dielectric layer includes a first surface. The stacking conductive structure is disposed on the first surface of the dielectric layer. The stacking conductive structure includes a first conductive layer disposed on the first surface of the dielectric layer, and a second conductive layer stacked on the first conductive layer. A first surface roughness of the first surface of the dielectric layer is larger than a second surface roughness of a top surface of the first conductive layer, and the second surface roughness of the top surface of the first conductive layer is larger than a third surface roughness of a top surface of the second conductive layer.

Abstract: A semiconductor device package includes a substrate, a semiconductor device and an encapsulant. The substrate includes a passivation layer, a first conductive layer and a barrier layer. The passivation layer has a substantially vertical sidewall. The first conductive layer is disposed on the passivation layer. The barrier layer is disposed on the passivation layer and the first conductive layer. The barrier layer includes a substantially slant sidewall.