Patents Assigned to Advanced Semiconductor Engineering
  • Publication number: 20210091042
    Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Publication number: 20210090965
    Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Hsu-Chiang SHIH, Cheng-Yuan KUNG, Hung-Yi LIN
  • Publication number: 20210090982
    Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Yu-Chang CHEN
  • Publication number: 20210091453
    Abstract: A semiconductor device package includes a dielectric layer and a stacking conductive structure. The dielectric layer includes a first surface. The stacking conductive structure is disposed on the first surface of the dielectric layer. The stacking conductive structure includes a first conductive layer disposed on the first surface of the dielectric layer, and a second conductive layer stacked on the first conductive layer. A first surface roughness of the first surface of the dielectric layer is larger than a second surface roughness of a top surface of the first conductive layer, and the second surface roughness of the top surface of the first conductive layer is larger than a third surface roughness of a top surface of the second conductive layer.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210090947
    Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The semiconductor substrate includes a dielectric layer, at least one first conductive trace, and a conductive via. The dielectric layer has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive trace is disposed adjacent to the first dielectric surface of the dielectric layer. The conductive via is disposed adjacent to the second dielectric surface of the dielectric layer and connected to the first conductive trace, where the conductive via and the first conductive trace are connected at a first interface leveled with about a half thickness of the dielectric layer.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210082795
    Abstract: A semiconductor device package includes a substrate, a semiconductor device and an encapsulant. The substrate includes a passivation layer, a first conductive layer and a barrier layer. The passivation layer has a substantially vertical sidewall. The first conductive layer is disposed on the passivation layer. The barrier layer is disposed on the passivation layer and the first conductive layer. The barrier layer includes a substantially slant sidewall.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Shun Sing LIAO
  • Publication number: 20210082836
    Abstract: A substrate structure includes a chip attach area and an upper side rail surrounding the chip attach area. The upper side rail includes an upper stress relief structure and an upper reinforcing structure. The upper stress relief structure surrounds the upper chip attach area. The upper reinforcing structure surrounds the upper stress relief structure. A stress relieving ability of the upper stress relief structure is greater than a stress relieving ability of the upper reinforcing structure. A structural strength of the upper reinforcing structure is greater than a structural strength of the upper stress relief structure.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Shun Sing LIAO
  • Publication number: 20210082853
    Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Sheng LIN, Chin-Li KAO, Hsu-Nan FANG
  • Publication number: 20210083628
    Abstract: A power amplifier circuit includes a current generator and a current mirror driver. The current generator has a first input connected to a first voltage supply and an output configured to generate a first current. The current generator includes a first transistor, a second transistor, a first resistor and a second resistor. The first transistor has an emitter connected to ground. The second transistor has a base connected to a base of the first transistor and an emitter connected to ground. The first resistor is connected between the first voltage supply and a collector of the first transistor. The second resistor is connected between the first voltage supply and a collector of the second transistor. The current mirror drive has a first input connected to the output of the current generator to receive the first current and an output configured to generate a second current.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Jaw-Ming DING
  • Publication number: 20210083388
    Abstract: A semiconductor device package includes a circuit layer and a first antenna structure. The circuit layer includes a first surface, and a second surface opposite to the first surface. The first antenna structure is disposed on the first surface and electrically connected to the circuit layer. The first antenna structure includes a first patch, a second patch, a third patch, a first dielectric layer and a second dielectric layer. The second patch is disposed on the first patch. The first dielectric layer has a first dielectric constant (Dk), and is disposed between the first patch and the second patch. The third patch is disposed on the second patch. The second dielectric layer has a second dielectric constant and is disposed between the second patch and the third patch. The first dielectric constant is smaller than the second dielectric constant.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210082788
    Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung Hao CHEN, Chin-Cheng KUO
  • Publication number: 20210082835
    Abstract: A semiconductor device package and a method for packaging the same are provided. A semiconductor device package includes a carrier, an electronic component, a buffer layer, a reinforced structure, and an encapsulant. The electronic component is disposed over the carrier and has an active area. The buffer layer is disposed on the active area of the electronic component. The reinforced structure is disposed on the buffer layer. The encapsulant encapsulates the carrier, the electronic component and the reinforced structure.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Che HUANG, Lu-Ming LAI
  • Publication number: 20210082782
    Abstract: A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Han WANG, Ian HU
  • Publication number: 20210082791
    Abstract: A lead frame includes a die pad having a pad top surface and a pad bottom surface opposite to the top pad surface, a plurality of leads, each having a top lead surface and a bottom lead surface opposite to the top lead surface and disposed around the die pad, and a first molding compound disposed between the die pad and each of the leads. The first molding compound exposes the top pad surface of the die pad by covering a portion of the periphery of the top pad surface of the die pad. A method for manufacturing the lead frame is also disclosed.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Ying-Chung CHEN, Hui-Chung LIU
  • Publication number: 20210076510
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Publication number: 20210074664
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Ming-Chi LIU, Yu-Ting LU, Kai-Chiang HSU, Che-Ting LIU
  • Publication number: 20210074669
    Abstract: A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shun-Tsat TU, Pei-Jen LO, Fong Ren SIE, Cheng-En WENG, Min Lung HUANG
  • Publication number: 20210074676
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
  • Publication number: 20210066208
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a first dielectric layer, a first semiconductor element, a second dielectric layer, and at least one first conducive via. The first dielectric layer has a first top surface, a first bottom surface opposite to the first top surface, and a first side surface extending from the first top surface to the first bottom surface. The first semiconductor element is disposed adjacent to the first top surface of the first dielectric layer. The second dielectric layer has a second top surface, a second bottom surface opposite to the second top surface, and a second side surface extending from the second top surface to the second bottom surface, where the second dielectric layer covers a top surface of the first semiconductor element and the first side surface of the first dielectric layer.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210068267
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Min Lung HUANG