Abstract: A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).
Type:
Grant
Filed:
October 31, 2022
Date of Patent:
February 4, 2025
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Sudhanva Gurumurthi, Vilas Sridharan, Majed Valad Beigi
Abstract: Provided is an indium phosphide substrate which has suppressed sharpness of a wafer edge when polishing is carried out from the back surface of the wafer by a method such as back lapping. An indium phosphide substrate, wherein when planes A each parallel to a main surface are taken in a wafer, the phosphide substrate has an angle ? on the main surface side of 0°<??110° for all of the planes A where a distance from the main surface is 100 ?m or more and 200 ?m or less, wherein the angle ? is formed by a plane B, the plane B including an intersection line of an wafer edge with each of the planes A and being tangent to the wafer edge, and an plane of each of the planes A extending in a wafer outside direction, and wherein in a cross section orthogonal to the wafer edge, the indium phosphide substrate has an edge round at least on the main surface side, and the edge round on the main surface side has a radius of curvature Rf of from 200 to 350 ?m.
Abstract: A system for performing a scan test of a processor core includes a scan test module and a processor including a processor core and an input/output die, where the input/output die is coupled to the processor core. The scan test module transmits, in parallel to the input/output die, scan test input data. A serializer/deserializer module of the input/output die receives the input data, serializes the input data, and transmits the serialized input data to the processor core. A serializer/deserializer module of the processor core receives the serialized scan test input data, deserializes the input data, receives result data generated in dependence upon the input data, serializes the result data, and transmits the serialized result data to the input/output die. The input/output die serializer/deserializer module receives the result data, deserializes the result data, and provides the result data to the scan test module. Error detection can be carried out through redundancy.
Abstract: A bond structure is provided. The bond structure includes a seed layer and a conductive structure. The conductive structure includes a via portion over the seed layer and a plurality of wires protruding from the via portion.
Type:
Application
Filed:
July 28, 2023
Publication date:
January 30, 2025
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: High purity carbon sorbent monoliths that are particularly effective for the adsorption and subsequent desorption of trace-contaminants, such as ammonia, are produced by 3D-printing polymer monoliths, carbonizing them, and subsequently activating them to produce an effective amount of at least one type of oxygen species on exposed carbon surfaces. The high purity carbon sorbent monoliths are vacuum-regenerable on a time scale of a few minutes.
Type:
Application
Filed:
August 27, 2024
Publication date:
January 30, 2025
Applicant:
ADVANCED FUEL RESEARCH, INC.
Inventors:
Joseph E. Cosgrove, Marek A. Wojtowicz, Michael A. Serio, Andrew E. Carlson
Abstract: The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.
Type:
Application
Filed:
July 25, 2024
Publication date:
January 30, 2025
Applicant:
Advanced Micro Devices, Inc.
Inventors:
Indrani Paul, Benjamin Tsien, James R. Magro
Abstract: A system and method for perceiving a 3-D environment by using a camera and a radar sensor are disclosed. In order to generate a 3-D feature map that is used to perceive an environment through the fusion of a camera and a radar sensor, the method of perceiving a 3-D environment may include extracting a two-dimensional (2-D) feature map from an image obtained by the camera and transforming the 2-D feature map into a feature map in a 3-D space by using first distance information extracted from the image and second distance information measured by the radar sensor.
Type:
Application
Filed:
November 6, 2023
Publication date:
January 30, 2025
Applicant:
Korea Advanced Institute of Science and Technology
Abstract: A temperature measuring method and apparatus based on creatine chemical exchange saturation transfer (CEST) imaging. The method comprises the following steps: (1) performing creatine CEST imaging on a creatine phantom, and analyzing a chemical shift of creatine relative to water in the creatine phantom; (2) fitting a mathematical relation between the chemical shift of the creatine relative to water and the temperature; and (3) performing CEST imaging on creatine in a sample, and calculating the temperature according to the mathematical relation, fitted in step (2), between the chemical shift of the creatine relative to water and the temperature. In the temperature measuring method, the creatine is taken as an endogenous reference, and highly-spatial-resolution, highly-sensitive, and non-invasive absolute temperature measurement can be implemented by means of temperature dependence of a CEST effect of Cr and water.
Type:
Application
Filed:
January 19, 2022
Publication date:
January 30, 2025
Applicant:
SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY
Inventors:
Lijuan Zhang, Chao Zou, Siqi Cai, Shihui Zhou, Yang Zhou, Hairong Zheng, Xin Liu
Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.
Abstract: A coupling configured to connect a first pipe to a plurality of pipes comprising a first end and a second end, wherein the second end is tapered and comprises a plurality of lateral ribs and a plurality of longitudinal ribs, wherein each of the plurality of longitudinal ribs comprises a pliable and wedge-like shape, and each of the plurality of longitudinal ribs tapers toward the second end.
Abstract: A method and electronic circuit for memory replacement are provided. The method for memory replacement includes generating an input signal in response to an event for a memory, providing the input signal to a time-varying circuit including a plurality of time-varying devices, generating an output signal by reading a value stored in at least one time-varying device among the plurality of time-varying devices, and determining a storage space for replacement, based on the output signal.
Type:
Application
Filed:
November 16, 2023
Publication date:
January 30, 2025
Applicant:
KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventors:
Shinhyun CHOI, Myoungsoo Jung, Hakcheon Jeong, See-On Park, Donghyun Gouk, Seonghyeon Jang
Abstract: The invention relates to a directional coupler, coupling high power and low power is used to replace existing two high-power directional couplers, thus reducing the cost and reducing the insertion loss of high-power radio frequency channels. The directional coupler cooperates with a control conditioning board, a splitter, a multi-path radio frequency power amplifier and a combiner to form the radio frequency power amplifier system, and the system is connected to a spectrometer; on one hand, by using a standard signal output by the spectrometer and a feedback signal of the directional coupler, nonlinearity caused by the power amplifier is corrected to achieve magnet-free linear radio frequency power amplification and anomaly protection; and on the other hand, the spectrometer can be used for monitoring the output power of the directional coupler and monitoring antenna matching, so as to provide dual protection for the radio frequency power amplifier system.
Type:
Application
Filed:
October 9, 2024
Publication date:
January 30, 2025
Applicant:
SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY
Inventors:
Hairong ZHENG, Xinwei RONG, Ye LI, Jiasheng WANG, Jifeng CHEN, Xing YANG
Abstract: An electronic device is disclosed. The electronic device includes an electronic component, an input/output (I/O) signal delivery circuit, and a power delivery circuit. The electronic component has a first surface and a second surface opposite to the first surface. The I/O signal delivery circuit is disposed under the first surface of the electronic component. The power delivery circuit is disposed over the second surface of the electronic component and configured to balance a warpage of the electronic device.
Type:
Application
Filed:
July 28, 2023
Publication date:
January 30, 2025
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Chiung-Ying KUO, Chun-Yen TING, Hung-Chun KUO, Jung Jui KANG, Chang Chi LEE
Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
Type:
Application
Filed:
October 15, 2024
Publication date:
January 30, 2025
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
Abstract: Implementations described and claimed herein provide paddle leads for dorsal root ganglia (DRG) stimulation and methods of implanting the same. In one implementation, the paddle lead has a small profile facilitating deployment into a target space in the neuroforamen dorsal to the DRG and below the vertebral lamina. A paddle body of the paddle lead may include a living hinge and/or a contoured profile to further facilitate implantation in the target space. For suture assisted deployment as well as to resist migration of the paddle lead once deployed, the paddle lead may include a suture loop configuration. The paddle lead further includes an electrode array having electrode contacts arranged in a two dimensional configuration pattern to create an electrical field optimized for stimulation of the DRG.
Abstract: A surface-enhanced Raman spectroscopy substrate includes a multi-stage nanolattice structure including a first nanolattice including silver (Ag), a second nanolattice including gold (Au), and a third nanolattice including platinum (Pt). The surface-enhanced Raman spectroscopy substrate may be used for detecting different target materials.
Type:
Application
Filed:
January 29, 2024
Publication date:
January 30, 2025
Applicant:
Korea Advanced Institute of Science and Technology
Inventors:
Yeonsik JUNG, Minjoon KIM, Gyu Rac LEE, Minjae KU
Abstract: A method of operating a back-up aiming system for an artillery device having at least one back-up aiming drive unit and an artillery unit for a vehicle. The back-up aiming system is operated at least in the event of a failure of a main aiming system of the artillery device. An activation signal is provided to an interface to a back-up aiming electronics unit, the activation signal being configured to activate the back-up aiming system. A setpoint signal is read via an interface to a detection device, wherein an alignment signal with a setpoint speed and/or a setpoint torque with respect to a movement of the artillery device is calculated and set from the setpoint signal of the at least one back-up aiming drive unit. At least one alignment signal is outputted for aligning the at least one back-up aiming drive unit after the step of reading.
Abstract: A bonding structure and a package structure are provided. The bonding structure includes a first pad and a plurality of first wires. The first pad has a top surface including a first region and a second region, wherein the second region is closer to an edge of the top surface of the first pad than the first region is. The first wires are on the top surface of the first pad, wherein a number of the first wires on the first region is greater than a number of the first wires on the second region.
Type:
Application
Filed:
July 28, 2023
Publication date:
January 30, 2025
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A polyurethane precursor-containing woody material that includes a woody raw material that is impregnated with a blocked isocyanate compound and a polyethylene glycol. The polyethylene glycol is represented by a formula: HO—(CH2—CH2—O), —H (n=1 to 12,000). The blocked isocyanate compound is a compound which is formed from an isocyanate compound and a blocking agent that protects an isocyanate group contained in the isocyanate compound, and is inactivated by a group derived from the blocking agent.
Type:
Application
Filed:
December 6, 2022
Publication date:
January 30, 2025
Applicant:
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
Abstract: A processor-implemented method with image analysis includes: receiving a test image; generating a plurality of augmented images by augmenting the test image; determining classification prediction values for the augmented images using a classifier; determining a detection score based on the classification prediction values; and determining whether the test image corresponds to anomaly data based on the detection score and a threshold.
Type:
Grant
Filed:
January 13, 2022
Date of Patent:
January 28, 2025
Assignees:
Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology