Abstract: A new fiber optic connector provides a very small form factor with reduced size. The fiber optic connector may comprise a single-body housing having a front end and rear end in a longitudinal direction, two ferrules accommodated in the housing and protruding from the front end of the housing, a back housing positioned adjacent to the rear end of the housing, two springs positioned between the two ferrules and the back housing to urge the two ferrules to move forward, and a boot assembly connected to the rear end of the housing. The housing comprises a latch arm extending obliquely upwards, and the latch arm is in a depressed state when the fiber optic connector is mating with an adapter.

Abstract: A germ-repellent plastic contains an anti-biofouling compound, and a basic plastic. The anti-biofouling compound is optionally selected from the group of a polyol, a polyether polyol, a polyol derivative, and a combination thereof; or the anti-biofouling compound is selected from the group consisting of a polyether, a poly (ethylene glycol) ether, a polysorbate, and a combination thereof; or the anti-biofouling compound is selected from the group consisting of poly (ethylene glycol) sorbitan monolaurate, poly (ethylene glycol) sorbitan monooleate, poly (ethylene glycol) sorbitol hexaoleate, ceteareth, and a combination thereof. The basic plastic is not a blend of a low-density polyethylene polymer and an ethyl vinyl acetate copolymer, a blend of a polypropylene polymer and an ethyl vinyl acetate copolymer, a blend of polyolefin elastomer polymers and a polyvinyl chloride polymer. A method for manufacturing such a germ-repellent plastic and a germ-repellent plastic item are also described.

Abstract: An MRAM cell includes a switch unit configured to determine opening and closing thereof by a word line voltage and to activate a current path between a bit line and a bit line bar in an opened state thereof, first and second MTJs having opposite states, respectively, and connected in series between the bit line and the bit line bar, to constitute a storage node, and a sensing line configured to be activated in a reading mode of the MRAM cell, thereby creating data reading information based on a voltage between the first and second MTJs, wherein the first and second MTJs have different ones of a low resistance state and a high resistance state, respectively, in accordance with a voltage drop direction between the bit line and the bit line bar, thereby storing data of 0 or 1.

Abstract: A system and method for fabricating on-die metal-insulator-metal capacitors capable of maintaining a similar capacitance for design reuse across multiple semiconductor fabrication processes are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. Subsequent semiconductor fabrication processes typically increase a number of metal plates that can be formed in the dielectric layer, such as an oxide layer, between two signal nets. To permit design reuse across multiple semiconductor fabrication processes, for a particular MIM capacitor designated to maintain a same capacitance, the additional metal plates for the particular MIM capacitor are formed as floating nets.

Abstract: A display panel and a display device are provided. The display panel includes a substrate, a driving circuit, and a first light blocking layer. The driving circuit includes an oxide transistor and a silicon transistor disposed at the substrate. The oxide transistor includes a first active layer. An orthographic projection of the first light blocking layer on the substrate at least overlaps an orthographic projection of the first active layer on the substrate.

Abstract: A semiconductor device package includes a substrate, a first antenna pattern and a second antenna pattern. The substrate has a first surface and a second surface opposite to the first surface. The first antenna pattern is disposed over the first surface of the substrate. The first antenna pattern has a first bandwidth. The second antenna pattern is disposed over the first antenna pattern. The second antenna pattern has a second bandwidth different from the first bandwidth. The first antenna pattern and the second antenna pattern are at least partially overlapping in a direction perpendicular to the first surface of the substrate.

Abstract: Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If the hit rate of a first portion is greater than a second threshold, then a second portion will have a non-bypass insertion policy since the cache is relatively useful in this scenario. However, if the hit rate of the first portion is less than or equal to the second threshold, then the second portion will have a bypass insertion policy since the cache is less useful in this case.

Abstract: A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.

Abstract: A nanoscale thin film structure and implementing method thereof, and, more specifically, a nanoscale thin film structure of which target structure is designed with quantized thickness, and a method to implement the nanoscale thin film structure by which the performance of the manufactured nanodevice can be implemented the same as the designed performance, thereby applicable to high sensitivity high performance electronic/optical sensor devices.

Abstract: A fuel tank venting system for an automotive vehicle comprising: a fuel tank comprising a vapor dome, a refueling pipe, a fuel vapor trap that is connected to the fuel tank by an inlet conduit, wherein the inlet conduit is connected with the fuel tank through an orifice which is permanently open, the orifice being arranged in the vapor dome of the fuel tank in a static condition and a normally closed shutter device that communicates with the atmosphere and that is connected to the fuel vapor trap by an outlet conduit, the normally closed shutter device comprising an electrically-actuated valve being closed when the electrically-actuated valve is de-energized, wherein the normally closed shutter device is configured to be open during vehicle refueling process and to be closed when the fuel in the fuel tank reaches a predetermined fill level and when the vehicle is in normal operation.

Abstract: A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.

Abstract: Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes executing at least one application in the dockable device using a first processor, and initiating an application migration for the at least one application from the first processor to a second processor in a docking station responsive to determining that the dockable device is in a docked state, wherein the at least one application continues to execute during the application migration from the first processor to the second processor.

Abstract: Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.

Abstract: A fitness tool for a user to use in performing stretching or other fitness activities may include a first member including (i) a first elongated shaft, the first elongated shaft including a first interface feature on a first end of the first elongated shaft, and (ii) a handle disposed at the second end. A second member may include a second elongated shaft, where the second elongated shaft may include a second interface feature at a first end of the second elongated shaft. The first and second interface features, when longitudinally engaged with one another, may enable the first and second shafts to rotate relative to one another. The second elongated shaft may include a hand or foot engagement mechanism.

Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.

Abstract: A semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening that extend between the first surface and the second surface and respectively expose the plurality of lateral surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate and a third portion disposed within the first opening and the second opening.

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

Abstract: Provided is a novel solid electrolyte material of high density and high ionic conductivity, and an all-solid-state lithium ion secondary battery that utilizes the solid electrolyte material. The solid electrolyte material has a chemical composition represented by Li7-3xGaxLa3Zr2O12 (0.08?x<0.5), has a relative density of 99% or higher, belongs to space group I-43d, in the cubic system, and has a garnet-type structure. The lithium ion conductivity of the solid electrolyte material is 2.0×10?3 S/cm or higher. The solid electrolyte material has a lattice constant a such that 1.29 nm?a?1.30 nm, and lithium ions occupy the 12a site, the 12b site and two types of 48e site, and gallium occupies the 12a site and the 12b site, in the crystal structure. The all-solid-state lithium ion secondary battery has a positive electrode, a negative electrode, and a solid electrolyte. The solid electrolyte is made up of the solid electrolyte material of the present invention.

Abstract: Predicates for processing in memory is described. In accordance with the described techniques, a predicate instruction to compute a conditional value based on data stored in a memory is provided to a processing-in-memory component. A response that includes the conditional value computed by the processing-in-memory component is received, and the conditional value is stored in a predicate register. One or more conditional instructions are provided to the processing-in-memory component based on the conditional value stored in the predicate register.

Abstract: Provided is a high-gain amplifier based on double-gain boosting including a first gain amplification unit including a first amplifier, a second amplifier, and a an interstage matching network connected between the first amplifier and the second amplifier and performing primary amplification; and a second gain amplification unit connected in parallel with the first gain amplification unit and performing secondary boosting.