Abstract: Provided is a semiconductor device, including: a compound semiconductor layer; a first insulating film provided on the compound semiconductor layer; a second insulating film, which is formed of a material different from the first insulating film, provided on the first insulating film; and a gate electrode provided above the second insulating film. The first insulating film may include tantalum oxynitride, and the second insulating film may include a material with a larger band gap than tantalum oxynitride. The second insulating film may include aluminum oxynitride.

Abstract: According to the present invention, a pulsed laser output section outputs a laser beam having a predetermined wavelength as first pulses. An optical path determining section receives the first pulses and determines one or more among two or more optical paths for each of the first pulses for output. A wavelength changing section receives light beams travelling, respectively, through the two or more optical paths and, when the power of the traveling light beams exceeds a threshold value, changes the light beams to have their respective different wavelengths for output. A multiplexer multiplexes outputs from the wavelength changing section. The optical path determining section allows for change in the power ratio between a first power of the light beam traveling through one of two among the two or more optical paths and a second power of the light beam traveling through the other of the two optical paths.

Abstract: An optical testing apparatus is used in testing an optical measuring instrument. The optical measuring instrument provides an incident light pulse from a light source to an incident object and receives a reflected light pulse as a result of reflection of the incident light pulse at the incident object. The optical testing apparatus includes two or more testing light sources, two or more optical penetration members, and a wave multiplexing section. The two or more testing light sources each output a testing light pulse. The two or more optical penetration members each have an optical penetration region and receive the testing light pulse from each of the two or more testing light sources for penetration through the optical penetration region. The wave multiplexing section multiplexes the testing light pulses penetrating through the two or more optical penetration members for provision to the optical measuring instrument.

Abstract: A stand-alone active thermal interposer device for use in testing a system-in-package device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

Abstract: Embodiments of the present invention provide systems and methods for performing tests on a device under test (DUT) based on training data derived from a set of training DUTs using nearfield measurement data. Nearfield measurement data can be mapped to performance metrics that approximate performance metrics derived from the far-field measurement data. Nearfield measurements can then be performed on a DUT to generate second nearfield measurement data, and performance metrics of the DUT are generated using the second nearfield measurement data and the mapped performance metrics derived from the training DUTs.

Abstract: A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

Abstract: Devices for testing a DUT having a circuit coupled to an antenna are disclose. The device can include a DUT location, a probe, and a ground area configured to serve as an antenna ground area for the antenna of the DUT. The ground area includes a slot that the antenna feed impedance is not affected or not affected significantly. The probe is adapted to weakly couple to the antenna of the DUT via the opening to probe a signal when the antenna of the DUT is fed by the circuit of the DUT and/or in order to couple a signal to the antenna which is fed to the circuit of the DUT by the antenna.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs.

Abstract: An electronic component handling apparatus that handles a pressed body including a DUT or a carrier accommodating the DUT, includes: a pressing device that electrically connects the DUT to a socket by pressing the pressed body toward the socket, and includes: a contact plate that contacts the pressed body; and a retainer that holds the contact plate, the contact plate being separated from the retainer while the contact plate contacts the pressed body, and the contact plate being held by the retainer while the contact plate is separated from the pressed body.

Abstract: A burn-in board includes: a board; sockets mounted on the board; a connector mounted on the board; and wiring systems disposed in the board and connecting the sockets and the connector. The wiring systems comprise: a first wiring system that transmits a first signal; and a second wiring system that transmits a second signal different from the first signal, and a type of a first connection form of the first wiring system is different from a type of a second connection form of the second wiring system.

Abstract: An electronic component handling apparatus handles a device under test (DUT). The electronic component handling apparatus includes: transfer units that each include a DUT transfer part that mounts the DUT on a first tray and removes the DUT from the first tray; contact units that each press the DUT mounted on the first tray against a socket disposed on a test head connected to a tester; and a tray transporter that transports the first tray between the contact units and the transfer units. Either or both of (i) at least one of the contact units and (ii) at least one of the transfer units are removably disposed on the electronic component handling apparatus.

Abstract: Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances.

Abstract: A sensor test apparatus capable of efficiently testing a sensor is provided. A sensor test apparatus 30 which tests the pressure sensor 90 includes an application unit 40 including an application device 42 including a socket 445 to which the sensor 90 is electronically connected, a pressure chamber 43 which applies pressure to the sensor 90, and a heat sink 443,462 which applies a thermal stress to the sensor 90, the test unit 35 which tests the sensor 90 via the socket 445, and the conveying robot 33 which conveys the sensor 90 into and out of the application unit 40.

Abstract: A test carrier that accommodates a device under test (DUT) and has a through-hole facing the DUT, including: a movable valve that: opens by suction through the through hole such that the DUT is sucked through the through hole.

Abstract: A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system for generating signals for input to the circuits and for processing output signals from the circuits for testing the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer thermal interposer (TI) layer operable to contact a second surface of the wafer and operable to selectively heat areas of the wafer, and a cold plate disposed under the wafer TI layer and operable to cool the wafer. The system further includes a thermal controller for selectively heating and maintaining temperatures of the areas of the wafer by controlling cooling of the cold plate and by controlling selective heating of the wafer TI layer.

Abstract: Embodiments of the present invention provide systems and methods for performing automated device testing at high power using ATI-based thermal management that substantially mitigates or prevents the pads and pins thereof from being burned or damaged. In this way, the lifespan of the testing equipment is improved and the expected downtime of testing equipment is substantially reduced, while also reducing cost of operation.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: A test carrier that accommodates a device under test (DUT) and has a through-hole facing the DUT, including: a movable valve that: opens by suction through the through hole such that the DUT is sucked through the through hole.

Abstract: An optical testing device for use in testing an optical measuring instrument provides incident light from a light source to an incident object and receives reflected light due to reflection of the incident light at the incident object. The optical testing device includes an incident light receiving section that receives incident light, and a light signal providing section. The light signal providing section provides a light signal to the incident object after a predetermined delay time since the incident light receiving section has received the incident light. A reflected light signal due to reflection of the light signal at the incident object is provided to the optical measuring instrument. The delay time is approximately equal to the time between emission of the incident light from the light source and reception of the reflected light by the optical measuring instrument in the case of actually using the optical measuring instrument.

Abstract: An electronic component testing apparatus that tests a DUT (device under test) disposed in a carrier includes: a test head including a socket; and an electronic component handling apparatus that presses the DUT in the carrier against the socket. The socket includes: contactors disposed to correspond to terminals of the DUT that are exposed to the socket via a first opening of the carrier; and a first wall projecting toward the carrier along a pressing direction of the DUT. The electronic component handling apparatus aligns the terminals with the contactors by pressing the DUT against the socket such that a first pressing mechanism of the carrier presses the DUT against the first wall.