Abstract: A duty-cycle generator including, in one embodiment, a duty-cycle adjustment circuit and a delay processor. The duty-cycle adjustment circuit is adapted to receive an input clock signal having an input duty cycle, generate first and second versions of the input clock signal having different amounts of delay, and combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle. The delay processor is adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal.

Abstract: Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required. A refresh flag can optionally be set if a refresh is required. The idle cycle sequence comprises one or more idle cycles. The idle cycle sequence can optionally be allocated within a predefined duration of the refresh flag being set. The step of determining step whether a refresh of the dynamic random access memory is required can be based on real-time or expected conditions.

Abstract: A line driver circuit with an output impedance that is set to a value which is based at least in part on the impedance of one or more current sources of the driver circuit. The current source impedance varies depending on the desired output amplitude of the driver circuit. Once the current source impedance is determined, a resistor is selected to be placed in parallel connection with the current source so that the combination of the resistor and the current source impedance will produce a desired output impedance for the driver circuit. Preferably, the driver circuit includes a second current source and second resistor in parallel with each other and a source termination resistor, such that the combination of the current source impedance values and the resistor values produces a desired output impedance for the driver circuit.

Abstract: Various apparatus and methods for controlling data for a redundant array of inexpensive/independent disks (RAID) are presented. For example, in one illustrative embodiment, a controlling apparatus can include a translation device composed substantially entirely of gate-level electronic hardware, wherein the translation device includes a sector sequencer capable of arranging sector units of target data and parity data on a plurality of N disks as a function of block location.

Abstract: Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change. The already placed chip design is pruned to create a set of valid flops and valid scan chains based on a set of pruning rules. A unified flop database is generated containing physical location and connection information for the new flops and the set of valid flops. A change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops is generated meeting allocation and placement sensitive signal connection rules. The new flops are connected to the selected valid flops allowing design for test requirements to be met.

Abstract: A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e.g., a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

Abstract: A method includes storing first and second sets of parameters in a register. Each set of parameters defines a storage transaction to store data to a computer readable medium or a retrieval transaction to retrieve data from the computer readable medium. The first storage or retrieval transaction is performed according to the first set of parameters. The second set of parameters is retrieved from the register automatically when the first storage or retrieval transaction is completed, without waiting for a further command from a control processor. The second storage or retrieval transaction is performed according to the retrieved second set of parameters. A system for performing the method and a computer readable medium containing pseudocode for generating an application specific integrated circuit that performs the method are provided.

Abstract: A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that electrical current is evenly distributed in the conductor, even at the edge regions of the conductor. This even distribution of rhombic slots ensures that electrical current is evenly distributed at least in the central region, and in most if not all cases, across the entire region of the conductor including the edge regions. Thus, the reverse fill pattern prevents current crowding. By preventing current crowding, more stringent metal distribution targets can be met without creating or exacerbating problems associated with IR drop and EM, and without having to add any extra metal to avoid such problems.

Abstract: Methods and apparatus are provided for performing Soft-Output Viterbi Algorithm (SOVA) detection at higher data rates than achievable with conventional designs.

Abstract: Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of the plurality of sub-matrices has a single entry. Each of the sub-matrices has at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, wherein one or more of the memory elements may be selectively disabled. The Phi-nodes may be selectively disabled, for example, at run-time. The Phi-node optionally further comprises a multiplexer in order to provide a variable parity check matrix.

Abstract: A channel optimization system for use with a communications channel and method of separating and encoding signals associated with the communications channel. In one embodiment, the channel optimization system includes an assorter that receives first and second signals having disparate transmission characteristics and selects one of the first and second signals. The channel optimization system also includes a translator, coupled to the assorter, that encodes the selected one of the first and second signals into a symbol representation as a function of a transmission characteristic associated therewith.

Abstract: The present invention provides a method for improved data communication and a transceiver employing the method. In one embodiment, the method includes generating data blocks to transmit to a second transceiver, generating identification data for the data blocks and identifying the data blocks transmitted to the second transceiver based on the identification data.

Abstract: Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization in the presence of a non-linear channel. A latch employed by a decision-feedback equalizer is positioned by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; determining a threshold position of the latch based on the samples; and transforming the determined position to address the non-linearity of the channel. For example, a non-linear mapping table can map measured threshold values to transformed threshold values based on distance.

Abstract: A system and method, associated with a receiver, for increasing the range or bandwidth of a wireless digital communication network and a receiver incorporating the system or the method. In one embodiment, the system includes: (1) a service class detector configured to determine a service class of a PDU received by the receiver from the wireless digital communication network and (2) a frame check sequence checker coupled to the service class detector and configured to disregard error-checking information in the PDU when the service class indicates that the PDU is a streaming media PDU.

Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.

Abstract: Methods and apparatus are provided for adaptively establishing the optimal sampling phase offset for a DFE operation. According to one aspect of the invention, one or more values in an amplitude domain are converted into a time domain, for example, using a phase detector, based on phase information to provide said sampling phase. The values in the amplitude domain optionally comprise one or more of detected DFE data, ?(n) and a sign of an error term for detected DFE data. The sampling phase can establish the phase of an independent clock or an offset to a second clock, such as a clock recovered from a received signal by a clock and data recovery (CDR) circuit.

Abstract: A self calibrating network comprises a first node and a second node. The first node transmits a calibration data packet. The second node receives the calibration data packet and determines a calibration value for the second node to optimize the transfer of data from the first node to the second node.

Abstract: A method and device for providing a communication session with a plurality of users. In one embodiment, the method includes: (1) transmitting an initiation message from the first terminal to the second terminal, the initiation message including a first address assigned to the first terminal, (2) dividing a display of the first terminal to simultaneously display text to be transmitted from the first terminal and text received from the second terminal, the dividing based on if there is text to be transmitted by the first terminal, (3) receiving the initiation message at the second terminal, (4) transmitting a first reply to the initiation message from the second terminal to the first terminal and (5) receiving the first reply at the first terminal.

Abstract: An apparatus and method are provided for extracting connection information from a traffic header in a communications network. The apparatus includes a first storage element containing a first look-up table for determining a first data packet header offset and data size for extracting a communications protocol type from the header and a second storage element containing a second look-up table for determining from the communications protocol type a second data packet header offset and second data size for extracting a connection address from the header. The storage elements may be in the form of content-addressable memories. Exception handling and hardware initialization can be controlled by a system processor.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.