Patents Assigned to Agere Systems
  • Patent number: 7671450
    Abstract: An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: March 2, 2010
    Assignee: Agere Systems Inc.
    Inventors: Ellis E. Nease, Ashley Rebelo, Christopher J. Wittensoldner
  • Publication number: 20100044767
    Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.
    Type: Application
    Filed: November 2, 2009
    Publication date: February 25, 2010
    Applicant: Agere Systems Inc.
    Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
  • Publication number: 20100045326
    Abstract: The invention, in one aspect, provides a semiconductor device (100), including transistors (105), dielectric layers (115, 120) located over the transistors (105), interconnects (122) formed within the dielectric layers (115, 120), and a test structure (130) located adjacent a hot-spot (125) of the semiconductor device (100) and configured to monitor a real-time operational parameter of at least one of the transistors (105) or interconnects (122).
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Applicant: Agere Systems Inc.
    Inventors: Vance D. Archer, III, Daniel P. Chesire, Warren K. Gladden, Seung H. Kang, Taeho Kook, Sailesh M. Merchant, Vivian Ryan
  • Patent number: 7667321
    Abstract: A wire bond circuit device has a circuit die in which substantially all of the input/output (I/O) pads are disposed along the outermost row of pads. A substrate onto which the die is disposed has wedges that are similarly arranged in rows, with the wedges used to carry I/O placed closest to the circuit die. As a result, lowest-tiered bond wire is used to connect the I/O-related pads to their respective wedges.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: February 23, 2010
    Assignee: Agere Systems Inc.
    Inventors: Ashley Rebelo, Todd Snider
  • Patent number: 7666750
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: February 23, 2010
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 7669110
    Abstract: Methods and apparatus are provided for determining survivor paths in a Viterbi detector, using a trace-ahead algorithm. A trellis memory is maintained having a depth L that stores L trellis stages, each of the L stages having a plurality, N, of trellis states; and a status memory is maintained for each of the N states of the trellis, wherein each entry in the status memory identifies a least recent trellis state stored in the trellis memory of a survivor path that begins at a given state on a side of the trellis associated with most recent states. A bit sequence of one or more of the survivor paths in the trellis is determined in an order that the bits are received by examining least and most recent trellis stages of the trellis and the status memory. One or fork memories maintain an indicator of whether a given fork is active; a list of active forks; a trellis position of active forks in the trellis; and a fork type of one or more forks in the trellis.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: February 23, 2010
    Assignee: Agere Systems Inc.
    Inventor: Nils Graef
  • Patent number: 7664267
    Abstract: An encryption device and method and decryption device and method which implement a bit-based encryption scheme and hardware design. The encryption device includes a random number generator, receiving a main key, determining a working key using at least one random number and outputting a working key, a model, receiving the main key, the working key and plain text to be encoded and generating at least two frequency counts. The encryption device further includes an encoder, which outputs encoded text based on the working key, the plain text and the at least two frequency counts. The encryption device and method and decryption device and method process encrypted text that is based upon a stream structure with an unlimited key length and may be compressed by 50%. The encoded text is changeable with different environments even for the same plain text and the same key. Operations of the hardware design are based on arithmetic additions and shifts, and not multiplications and divisions.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: February 16, 2010
    Assignee: Agere Systems Inc.
    Inventors: Chenggang Duan, Fengguang Zhao, Sunil K. Gupta
  • Publication number: 20100037188
    Abstract: Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.
    Type: Application
    Filed: February 3, 2009
    Publication date: February 11, 2010
    Applicant: Agere Systems, Inc.
    Inventors: Joseph J. Jamann, James C. Parker, Vishwas M. Rao
  • Publication number: 20100032766
    Abstract: A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance.
    Type: Application
    Filed: June 2, 2006
    Publication date: February 11, 2010
    Applicant: Agere Systems Inc.
    Inventors: Alan Sangone Chen, Mark Victor Dyson, Edward Belden Harris, Daniel Charles Kerr, William John Nagy
  • Patent number: 7660064
    Abstract: A hard disk drive write driver circuit is described that can change the output impedance of the write driver by use of a lookup table of control values. A control value is selected from the lookup table by using an address based on a dynamic system variable and a program controlled value. The dynamic system variable is converted to a digital representation. The digital representation and a portion of the program controlled value are used as an address to the lookup table to select a control value. The write driver is responsive to the selected control value to control overshoot current. A method to digitally program the output impedance of a preamp write driver based on realistic operating data is also discussed. An additional approach to controlling overshoot current in a write driver through digital control of overshoot duration is also described.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: February 9, 2010
    Assignee: Agere Systems Inc.
    Inventors: James Patrick Howley, Michael Philip Straub
  • Patent number: 7660916
    Abstract: The present invention utilizes a single DMA engine to process the requests of active DMA channels competing for transfer of data over a single bus. The invention employs two identical sets of DMA request registers which are connected to a processor. These register sets are connected through a switching means to the DMA engine. While a first DMA transfer represented by a first set of registers is active, the process enables preparation of the next request in a second set of registers. Upon completion of the first DMA transfer, the DMA engine is switched to commence processing of the DMA request represented by the second set of registers.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: February 9, 2010
    Assignee: Agere Systems Inc.
    Inventors: Anatoly Moskalev, Parakalan Venkataraghaven
  • Publication number: 20100027592
    Abstract: In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 4, 2010
    Applicant: Agere Systems Inc.
    Inventors: Eliahou Arviv, Daniel Briker, Gennady Zilberman
  • Publication number: 20100027611
    Abstract: In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fibre Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Applicant: Agere Systems, Inc.
    Inventors: Xingdong Dai, Geoffrey Zhang, Gary Schiessler, Dwight Daugherty, Mohammad Mobin, Lane Smith, Dennis Farley, Max Olsen
  • Publication number: 20100026378
    Abstract: Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
    Type: Application
    Filed: February 3, 2009
    Publication date: February 4, 2010
    Applicant: Agere Systems, Inc.
    Inventors: James C. Parker, Vishwas M. Rao, Clayton E. Schneider, JR., Gregory W. Sheets, Prasad Subbarao
  • Publication number: 20100027606
    Abstract: In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fibre Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Applicant: Agere Systems, Inc.
    Inventors: Xingdong Dai, Geoffrey Zhang, Max Olsen, Dwight Daugherty
  • Patent number: 7657858
    Abstract: A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least one power ring. The step of determining a location of at least one connection between the ESD structure and at least one power ring may include the steps of determining a minimum spanning tree of elements associated with a given power ring; and back-tracing through a minimum spanning tree of elements associated with a given power ring in order to determine a minimal list of routed paths among the elements.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: February 2, 2010
    Assignee: Agere Systems Inc.
    Inventors: Youang Pin Chen, Sireesha Tulluri Lakshmi Naga Venkata Srujana, Nirav Patel, Raghunatha Reddy Lakki Reddy, Sivaramakrishnan Subramanian, Venkat Rao Vallapaneni
  • Patent number: 7656255
    Abstract: Methods and apparatus are provided for programmable active inductance. The disclosed active inductor devices provide a tunable bandwidth with improved linearity. The disclosed active inductors have a variable frequency response corresponding to a variable inductance of the active inductor. The active inductor comprises a variable resistive circuit having an effective resistance, wherein the variable resistive circuit is comprised of at least one resistor that can be selectively bypassed in the variable resistive circuit to vary the effective resistive. The active inductor has an inductance that can be varied by varying the effective resistance.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: February 2, 2010
    Assignee: Agere Systems Inc.
    Inventors: Christopher J. Abel, Robert J. Kapuschinsky, Gary D. Polhemus
  • Patent number: 7656959
    Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: February 2, 2010
    Assignee: Agere Systems Inc.
    Inventor: Erich Franz Haratsch
  • Patent number: 7657222
    Abstract: A wireless cable networking gateway, a method of wireless cable networking and a Wi-Fi system incorporating the gateway or the method. In one embodiment, the gateway includes: (1) a wireless transceiver for transferring data between wireless and wireline domains, (2) wide-area and premises cable interfaces for coupling the wireless cable networking gateway to respective wide-area and premises cable networks and (3) channel insertion and extraction circuitry, coupling the wireless transceiver, the wide-area cable interface and the premises cable interface, that routes the data between the wireless transceiver and at least a portion of a television channel to be transmitted across at least the premises cable interface, remaining television channels being transmitted from the wide-area cable interface to the premises cable interface.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: February 2, 2010
    Assignee: Agere Systems Inc.
    Inventor: Joseph N. Alba
  • Patent number: 7657754
    Abstract: Apparatus and methods are presented for protecting data in microcontrollers from both malicious software processes running inside the device as well as from unauthorized attempts to read the data from an external data bus and/or external memory. An illustrative embodiment of the invention accomplishes these security improvements, in part, by utilizing an enhanced memory management unit (MMU). The enhanced MMU is configured to prevent one software process running on the microcontroller from accessing data associated with a different software process running on the same microcontroller. Moreover, data transmitted over an external data bus or stored in an external memory is encrypted, thereby reducing the chances that unauthorized users will gain exploitable information from this data.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: February 2, 2010
    Assignee: Agere Systems Inc
    Inventors: Michael Joseph Chambers, Michael Kiessling, Kenneth A. Tuchman, Hai Wang