Abstract: A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow of etchant gas into the chamber is controlled in response thereto.

Abstract: A method of generating an aggregate frame having a header unit, which carries MAC-header information applicable to one or more data units of said aggregate frame. Since each data unit of the aggregate frame no longer needs to carry the full MAC-header information, the overhead associated with the MAC header can be significantly reduced. At the receiver, the full MAC header corresponding to the data unit is reconstructed by (i) matching the appropriate header and data units to one another and (ii) combining the information present in the header unit and the compressed header portion of the data unit. Embodiments of the present invention are capable of improving the data throughput, for example, in an entertainment network having paired source and destination devices (e.g., a DVD player and an LCD screen) with a relatively large amount of data streamed from the former to the latter.

Abstract: The present invention provides a method for transmitting data and a transceiver. In one embodiment, the method includes: (1) generating data blocks of a data package in a first transceiver to transmit to a second transceiver, the first transceiver including a micro-controller coupled to a digital signal processor, (2) generating identification data in the first transceiver for the data blocks, wherein the identification data is an index of a list of the data blocks to be transmitted and each of the data blocks is transmitted with the index and (3) identifying the data blocks to be transmitted to the second transceiver based on the identification data, wherein the microcontroller employs the index to manage transmission of the data blocks.

Abstract: A fast switching, dual frequency phase locked loop comprising dual phase/frequency detectors, dual charge pumps, a pair of loop filters, and a low leakage voltage controlled oscillator. Each phase/frequency detector and associated tuning ports of the voltage controlled oscillator can be activated and deactivated separately without disturbing the charge on the loop filters.

Abstract: An apparatus and method for determining a resistance of a magneto-resistive head. A current drawn by the head, in response to a fixed bias voltage across the head, is converted to a zero temperature coefficient current such that when supplied to a resistor connected to an input terminal of a comparator the effects of variations in the resistance value are avoided. An output signal of the comparator indicates the resistance of the magneto-resistive head.

Abstract: A method and apparatus for embedding over-limit voltage detector and recording mechanisms on the silica wafer of integrated circuits to detect, protect and record voltage overages of pre-set voltage limits is presented. A detector circuit and a recorder circuit are placed in series or in parallel on the electrical connections between the integrated circuit devices and the voltage pins connected to outside power sources. When a voltage source is connected and an over-voltage condition is detected, the detector circuit short-circuits the connection while the recorder circuit records the event for later investigation.

Abstract: In one embodiment, an HSDPA co-processor for 3GPP Release 6 Category 8 (7.2 Mb/s) HSDPA that provides all chip-rate, symbol-rate, physical-channel, and transport-channel processing for HSDPA in 90 nm CMOS. The co-processor design is scalable to all HSDPA data rates up to 14 Mb/s. The coprocessor implements an Advanced Receiver based on an NLMS equalizer, supports RX diversity and TX diversity, and provides up to 6.4 dB better performance than a typical single-antenna rake receiver. Thus, 3GPP R6 HSDPA functionality can be added to a legacy R99 modem using an HSDPA co-processor consistent with embodiments of the present invention, at a reasonable incremental cost and power.

Abstract: The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and/or production phases of any equipment containing flash memory devices and also saving time during an updating or upgrading procedure of such an equipment already being in use. Accordingly, the invention proposes for programming a flash memory device to program only differences in information between data already stored in the flash memory device and new data to be stored.

Abstract: In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.

Abstract: Various different approaches are provided for conversion of analog signals to digital signals. For example, various partially clocked, multi-step analog to digital converters are discussed. Such analog to digital converters include a clocked fine conversion stage, a clocked coarse conversion stage, and a clock circuit. The fine conversion stage includes a first group of comparators clocked by a first clock and a second group of comparators clocked by a second clock. The first group of comparators is operable to compare an input voltage with a first fine reference voltage range, and the second group of comparators is operable to compare the input voltage with a second fine reference voltage range. The coarse conversion stage includes a group of clocked comparators that are operable to compare the input voltage with a coarse reference voltage range. The clock circuit selectably asserts one of the first clock and the second clock based at least in part on an output of the second conversion stage.

Abstract: A method and apparatus for detecting signal peaks caused by a thermal asperity event in a magnetic recording media to reduce data reading errors introduced by the thermal asperity event. A common mode voltage is determined for differential signals representing data bits read from the magnetic recording media and a threshold voltage produced responsive to the common mode voltage. A comparator determines if either of the differential signals exceeds the threshold voltage, thereby indicating the occurrence of a thermal asperity event.

Abstract: Disclosed is a current mode switched power supply. The current mode switched power supply includes a switching element and a power stage coupled to the switching element and configured to provide, in response to the switching of the switching element, an output voltage and a feedback voltage related to the output voltage. The current mode switched power supply also includes a digital control circuit connected to the switching element to digitally control the switching of the switching element.

Abstract: An apparatus for interfacing with a cell delay variation buffer and a re-assembly memory buffer includes a header and sequence number processing module that can interface with the cell delay variation buffer and a re-assembly processing module that can interface with the re-assembly memory buffer. The header and sequence number processing module causes payloads from the cells to be stored in annotated form in the cell delay variation buffer and then extracted. Payload information from the extracted annotated payload can be passed to the re-assembly processing module which causes it to be stored in the re-assembly memory buffer and extracted therefrom as needed. By splitting the cell delay variation and re-assembly buffer functions, less expensive commodity memory can be used for the cell delay variation buffer function.

Abstract: A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

Abstract: Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload integrity check, wherein a payload for each of the T protection packets are formed from corresponding symbols in the M-T data packets. An error correction decoding method is also provided that receives a plurality of error-free packets and one or more packets having an error; and reconstructs the one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode the received packets.

Abstract: A method for forming high density emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes. The emission elements formed according to the present invention provide a more uniform emission of electrons. Further, a display incorporating emission elements formed according to the present invention provides increased brightness. The reliability of the display is increased due to the use of a plurality of emission elements to supply electrons for stimulating the phosphor substrate material to produce the image.

Abstract: One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report.

Abstract: Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the integrated circuit based at least in part on the input dataset; generating a file including connectivity information and dimensional characteristics for extracted devices and parasitic elements associated with at least the identified ESD devices in the integrated circuit; identifying at least one ESD test based on the identified ESD devices and on connectivity to the identified ESD devices; and performing a linear network analysis for each identified ESD test based at least in part on the file.

Abstract: Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.

Abstract: Apparatus and method to allow retrieval of voice messages deleted from the voice message memory of a voice messaging system. A voice messaging system such as a telephone answering device includes a deleted voice message memory for storing voice messages deleted from the voice message memory. The deleted voice messages stored in the deleted voice message memory are retrievable by the user for review subject to rules for permanent deletion of the deleted voice messages (e.g., after a period of time, when the deleted voice message memory approaches capacity, periodically, etc.