Abstract: An RF coupler implementable as an integrated circuit includes a first transmission line having a first line portion and a second line portion. A first end of the first transmission line is coupled to an input port for receiving an RF input signal. A second end of the first transmission line is coupled to an output port for providing an RF output signal. The RF coupler further includes a second transmission line formed between the first line portion and the second line portion such that magnetic field produced due to the RF input signal in the first line portion and the second line portion envelops the second transmission line. A first end of the second transmission line is configured as a coupled port for providing a coupled RF signal, and a second end of the second transmission line is coupled to a termination element to form an isolation port.

Abstract: A protection circuit for an electronic circuit. The protection circuit includes a first transistor, a second transistor, a base current path, and a current discharge path. The first transistor is connected to a first terminal of the electronic circuit. The second transistor is connected to a second terminal of the electronic circuit. The first transistor is connected to the second transistor forming the base current path. The current discharge path conducts a discharge current from the first terminal to the second terminal through the second transistor when the second transistor is turned on with a base current in the base current path.

Abstract: A self ESD protected RF transistor. The RF transistor is connected to a sub-circuit which causes the RF transistor to self-protect from ESD damage. The sub-circuit triggers the RF transistor to clamp a positive polarity ESD pulse to ground/emitter terminal. The sub-circuit also shunts a negative polarity ESD pulse to ground.

Abstract: A combiner coupled to output terminals of a Doherty amplifier, the combiner comprising an inverter circuit and a transformer circuit. The inverter circuit comprising at least a first network and a second network, wherein each of the first network and the second network includes lumped elements. The transformer circuit comprising at least a third network and a fourth network, wherein each of the first third and the fourth network includes the lumped elements, wherein the lumped elements are selected from the group of capacitors and inductors.

Abstract: An output matching circuit for electronic amplifiers in the form of an integrated circuit is disclosed. The integrated circuit includes a first circuit, a second circuit, and a power sampling coupler. The first circuit is coupled to output of a first amplifier. The first circuit comprises a first matching section and an impedance inverter. The second circuit is coupled to output of a second amplifier, wherein the second circuit comprises a second matching section. The power sampling coupler is coupled to the first circuit and the second circuit, wherein the first circuit, the second circuit, and the power sampling coupler are fabricated as a single integrated circuit.

Abstract: A direct current to direct current (DCDC) voltage converter is described comprising a controller and at least one converter circuit. The converter circuit comprises at least first and second inductors, each having an input and an output; a first input switch connected to the input of the first inductor; a second input switch connected to the input of the second inductor; and an output switch connected to the outputs of the inductors for selectively combining the outputs to form a parallel combination of the inductors or a series combination of the inductors. The controller generates signals for selectively connecting the first and second input switches and the output circuit between a pair of power supply input terminals and a pair of power supply output terminals. In response to appropriate signals from the controller, the converter circuit can be operated as a buck converter or a boost converter.

Abstract: A DC-DC converter, capable of operation in either a boost or buck mode, includes a voltage source connected to an input switch through an inductive element such that a closed loop is formed. The DC-DC converter includes a switching network that receives one or more clock signals from an external clock source. The switching network has a first terminal connected to the inductive element, a second terminal connected to a first capacitor, and a third terminal connected to a second capacitor, wherein the switching network enables charging of the first capacitor and the second capacitor based on one or more clock signals such that the first capacitor and the second capacitor are charged alternately. The DC-DC converter includes a filter connected to a fourth terminal of the switching network, wherein the first capacitor and the second capacitor discharge alternately based on the one or more clock signals through the filter.

Abstract: A protection circuit for an electronic circuit. The protection circuit comprises at least three diodes connected in series in such a manner that an anode terminal of a first diode is connected to a cathode terminal of a second diode to form a ring. A first terminal is connected between diodes of a first pair of consecutive diodes of the ring. A second terminal is connected between diodes of a second pair of consecutive diodes of the ring. The position of the first terminal is fixed and the position of the second terminal is selectable in such a manner that a pre-determined turn-on voltage of the at least three diodes is obtained. The diodes are formed under one or more bond pads of the electronic circuit.

Abstract: A protection circuit for electronic circuitry comprising at least three diodes connected in series in such a manner that an anode terminal of a first diode is connected to a cathode terminal of a second diode to form a ring. A first terminal is connected between diodes of a first pair of consecutive diodes of the ring. A second terminal is connected between diodes of a second pair of consecutive diodes of the ring. The position of the first terminal is fixed and position of the second terminal is selectable in such a manner that a pre-determined turn-on voltage of the at least three diodes is obtained.

Abstract: An output matching network comprising a plurality of impedance matching circuits. The inputs of each of the plurality of impedance matching circuits are connected to a first input of the output matching network. The outputs of each of the plurality of impedance matching circuits are connected to a plurality of first outputs of the output matching network. One of the plurality of impedance matching circuits is active at a given time. The active impedance matching circuit of the plurality of impedance matching circuits exhibits a first input impendence at a first frequency band. Each inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a second input impedance at the first frequency band. The second input impendence is at least 10 times greater than the first input impendence.

Abstract: A radio frequency (RF) coupling circuit for coupling an RF output of a quadrature combined amplifier. According to an embodiment, the RF coupling circuit includes a phase shifting component and a coupling network. The phase shifting component provides a predetermined phase shift to an RF signal at a first output terminal of the quadrature combined amplifier. The coupling network combines the phase shifted first output signal with an RF signal at a second output terminal of the quadrature combined amplifier.

Abstract: A circuit exhibiting rectification and amplification characteristics. In particular, a full-wave rectifier, wherein the rectifier has the ability to simultaneously amplify and rectify an input voltage. The circuit comprises transconductor circuit, rectifying circuit and amplifying circuit. The transconductor circuit is adapted for receiving an input voltage from at least one voltage source. The input voltage is then converted into intermediate currents by the transconductor circuit. Thereafter, the rectifying circuit rectifies the intermediate currents current to produce a rectified current. Lastly, the amplification circuit amplifies the input voltage to produce the amplified voltage.

Abstract: A system for compensating impedance mismatch at an output terminal of a RF power amplifier is disclosed. In an embodiment, the system includes a plurality of samplers to measure a first set of parameters associated with an amplified signal being generated by the power amplifier. The first set of parameters is transmitted to a processing unit. The processing unit varies an impedance of an impedance element based on the first set of parameters. The impedance element is connected to the output terminal of the power amplifier.

Abstract: An improved current mirror circuit. The current mirror circuit includes a current mirror base network, a current source transistor, and an error transistor. The current mirror base network includes a first terminal, a second terminal, and a third terminal. The first terminal is connected to the current source transistor through a first impedance element. The second terminal is connected to the error transistor. The third terminal is connected to a first bias voltage source, and the first terminal is connected to a second bias voltage source.

Abstract: A low leakage logic circuit. The low leakage logic circuit includes a control circuit for logic circuit. The control circuit has a first transistor, a second transistor, a third transistor, a first diode, a first resistor and a second resistor. When the control circuit is ON, a first circuit path in the logic circuit is supplied with a first voltage from the source terminal of the third transistor. This voltage acts as a logic output and has the ability to source current at output terminal of the logic circuit. When the control circuit is OFF, a second circuit path in the logic circuit is supplied with a second voltage from the control circuit which is lower than the turn-on voltage of the second circuit path. This voltage is insufficient to turn ON the logic circuit, hence no current flows into the logic circuit.

Abstract: A current limiting circuit includes a power amplifier receiving an input signal through an attenuator. The power amplifier comprises one or more amplification stages and an output stage. The output stage is connected to an antenna. A mirror circuit is connected in parallel to the output stage. The magnitude of a first current flowing through the mirror circuit is proportional to the magnitude of a second current flowing through the output stage. Further, the current limiting circuit includes a comparator that compares the magnitude of the first current with a reference value to generate a control signal. The attenuator adjusts the power of the input signal based on the control signal thereby limiting the magnitude of the second current.

Abstract: A multi-mode RF power amplifier circuit that operates under dynamic power supply conditions. The power amplifier circuit operates under a high power mode and a low power mode. The multi-mode RF power amplifier includes a low power path and a high power path. Under the high power mode of operation, the high power path becomes active and the low power path becomes inactive. Each of the low power path and the high power path includes impedance matching networks and power amplifiers. Under either mode of operation, an inactive path will present at least five times higher input impedance than that of an active path. An impedance matching network connected between output terminals of the high power path and the low power path provides isolation between the output terminals of the high power path and the low power path.

Abstract: A quadrature amplifier comprises first and second amplifiers, each having an input and an output, a signal splitter connected to the inputs of the two amplifiers, a signal combiner connected to the outputs of the two amplifiers, and an impedance transformer connected to the output of the signal combiner. The signal splitter is a ?3 dB hybrid that splits an input signal into two output signals of equal amplitude that are in phase quadrature. The signal combiner is a ?3 dB hybrid that combines the output signals at the outputs of the two amplifiers. Since the output signals are in phase quadrature, the signals are combined to produce an inphase signal. The impedance transformer matches the output signal to an impedance of approximately 50 Ohms. Capacitive and resistive tuning networks connected to the ports of the signal combiner allow for adjustment of the center frequency and impedance of the signal combiner.

Abstract: A power amplifier having a driver stage and an output stage is configured to provide an amplified RF input signal. The driver stage of the power amplifier consists of one or more driver circuits consisting of a network of transistors, current sources, capacitive elements and resistive elements. An RF input signal is fed into the driver stage which is configured to provide a dynamic DC bias and an RF signal gain to a base terminal of a Bipolar Junction Transistor (BJT) power device present in the output stage. The output stage includes of a network of transistors, capacitive and resistive elements and when driven by the DC bias and the RF signal from the driver stage produces an amplified RF input signal at an output side of the output stage.

Abstract: A Multi-Mode Multi-Band (MMMB) radio frequency (RF) power amplifier circuit operating at multiple frequency bands. The power amplifier circuit comprises a single wideband power amplifier having high output impedance which is configured to be equal to a load impedance of the load connected to the power amplifier circuit. A bias voltage applied to the wideband power amplifier is changed from a first value to a second value to provide a predetermined output power of the wideband power amplifier to the load with the output impedance of wideband power amplifier being equal to the load impedance. The power amplifier circuit also includes an individual harmonic filter for filtering each frequency band independently.