Abstract: A power control circuit for regulating an output voltage applied to a radio frequency power amplifier. The power control circuit includes an amplifier, a pass transistor and one or more saturation detectors. An input ramp voltage having a magnitude equal to a first voltage level is applied to a negative terminal of the amplifier. The pass transistor provides an output voltage at a drain terminal of the pass transistor. The saturation detector detects a magnitude of a voltage at a gate terminal of the pass transistor and generates a control current based on the magnitude of the voltage at the gate terminal of the pass transistor. The voltage regulating circuit reduces the magnitude of the input ramp voltage from the first voltage level to a third voltage level based on the control current.

Abstract: A protection circuit for a power amplifier connected as a negative feedback loop around the power amplifier. The negative feedback loop comprises a detector circuit, a driver circuit and an attenuator circuit. The detector circuit receives output voltage from the power amplifier and generates a signal when the output voltage exceeds a predefined threshold. The driver circuit filters the signal received from the detector circuit to maintain feedback loop stability and adjusts the feedback loop bandwidth and gain to provide a filtered signal. The attenuator circuit receives the filtered signal and attenuates the input voltage of the power amplifier to reduce the output voltage of the power amplifier to a level below the predefined threshold.

Abstract: A multi-stage RF/Microwave power amplifier circuit is provided that is capable of operating efficiently at multiple output power levels. The amplifier comprises first and second amplifying stages, an output impedance matching network connected to the output of first amplifying stage and an interstage impedance matching network connected between the outputs of said first and second amplifying stages. In a high power mode, the first amplifying stage is enabled and the second amplifying stage is disabled and the output and interstage impedance matching networks present a first value of the output impedance that improves the efficiency of the first amplifying stage. In a low power mode, the first amplifying stage is disabled and the second amplifying stage is enabled, and output and interstage impedance matching networks present a second value of the output impedance that improves the efficiency of the second amplifying stage.

Abstract: A temperature-compensated power detector for detecting variations in the power level of an RF signal. The temperature-compensated power detector includes a detector circuit and a temperature compensating circuit. The detector circuit detects the power level of an RF signal and provides an output voltage that corresponds to the power level of the RF signal. The temperature compensating circuit ensures that the output voltage of the temperature-compensated power detector is independent of changes in the temperature.

Abstract: A method and system for optimizing a test plan of an Integrated Circuit (IC). The test plan includes two or more test sequences. A test sequence includes the measurement of a parameter of the IC. The total test time of the IC is reduced by performing one or more activities during a desired wait time associated with the measurement of the parameter. The test plan may be further optimized by modifying the one or more activities performed during the desired wait time.

Abstract: A low-loss Radio Frequency (RF) switch for high-power RF signals. The RF switch includes a first-biasing circuit connected to a first transistor and a second-biasing circuit connected to a second transistor. The RF switch switches its output signal between a first input signal and a second input signal. The first transistor is in a conduction state and the second transistor is in a non-conduction state when the first input signal is to be conducted to the output signal. The first-biasing circuit biases the first transistor at a first voltage for increasing conduction of the first input signal and the second-biasing circuit biases the second transistor at a second voltage for decreasing conduction of the first input signal. Moreover, the second transistor is in a conduction state and the first transistor is in a non-conduction state when the second input signal is to be conducted to the output signal.

Abstract: A system and method for frequency conversion in a frequency-conversion receiver is disclosed. The frequency-conversion receiver receives input RF signals carrying multiple channels. The frequency-conversion receiver converts the input RF signals to a wide IF band. The IF band is further processed by dividing the IF band into one or more frequency segments or by selecting a wideband frequency segment from the IF band. The wideband frequency segment or the one or more frequency segments are further down-converted, filtered and amplified to provide desired output IF signals, based on the number of channels required in the output IF signals.

Abstract: A circuit and method for tracking a local oscillator signal frequency in an RF tuner, for tuning input RF signals. The RF tuner includes a frequency-dependent impedance generator that generates a frequency-dependent impedance at the input by rejecting unwanted input RF signals and shunt feeding back the desired signal to the input. The desired signal frequency is centered at the local oscillator signal frequency. The frequency-dependent impedance generator is used with an amplifier circuit to generate a tracking amplifier, the frequency-dependent amplifier gain of which tracks the local oscillator signal frequency.

Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.

Abstract: The invention provides a system for providing tunable balanced loss compensation in an electronic filter. Tunable balanced loss compensation is provided by using cross-connected balanced transconductors and self-connected balanced transconductors. The cross-connected balanced transconductors and the self-connected transconductors compensate the unbalanced loss across the electronic filter. The self-connected balanced transconductors compensate the balanced loss across the electronic filter. Further, the cross-connected and the self-connected balanced transconductors are tunable by adjusting the values of their transconductances, thereby providing tunable balanced loss compensation.

Abstract: A compact ESD protection device is described that uses the reverse breakdown voltage of a base-emitter junction as a trigger diode to switch a transistor that shunts the forward bias ESD current to ground. The trigger diode in series with a leakage diode provides a path to shunt the reverse bias ESD current to ground. The leakage diode is matched to the trigger diode to shunt any leakage current from the trigger diode to ground.

Abstract: A voltage regulator for providing a regulated voltage is disclosed. The voltage regulator comprises an error amplifying module and a regulator. The error amplifying module provides a reference voltage, based on an output voltage to be regulated. The regulator provides a regulated output voltage based on the reference voltage. Voltage regulator provides stable output voltage against variations caused by power supply and load with a defined temperature coefficient.

Abstract: A method and circuit system for improving power efficiency of RF power amplifiers is disclosed. A preferred embodiment comprises a power amplifier comprising: a plurality of amplifier stages, a power regulator providing an output supply voltage at an output node responsive to an adjustable power control signal, wherein the output supply voltage is applied to at least one stage of a power amplifier; and an amplifier biaser providing a bias signal corresponding to the adjustable power control signal, wherein the output supply voltage and the bias signal are independently generated as functions of the adjustable power control signal.

Abstract: A power amplifier for use in wireless communication devices is disclosed that reduces the noise generated at the output of the amplifier in the receive band of the wireless communication device. A resonant circuit is inserted between the base ballast resister and the lumped resister. The resonant frequency of the resonant circuit is adjusted to correspond to the frequency offset between the transmission frequency and the frequency corresponding to the peak noise in the receive band of the communication device.

Abstract: A distortion cancellation amplifier is described having a main amplifier and an error amplifier. The main amplifier, in response to an input signal, generates an output signal having an amplified signal component and a distortion signal component. The error amplifier is sized and biased to generate, in response to the same input signal, a distortion signal component that has substantially the same magnitude as the distortion signal component of the main amplifier. The distortion signal component from the error amplifier is subtracted from the output signal of the main amplifier.

Abstract: An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.

Abstract: The invention provides a system and method for tuning broadband signals by using post mixer I/Q equalization. An Image Rejection Mixer (IRM) is used for mixing Radio Frequency (RF) signals and rejecting image signals from the desired RF signals. The IRM includes an I/Q mixer and a filter. The I and Q paths resulting from the mixing operation in the I/Q mixer are equalized in amplitude and phase by an I/Q equalizer. Thereafter, the image signals are rejected from the desired RF signals using the filter.

Abstract: A power amplifier has a plurality of amplifier stages. One or more predistorters are each placed between amplifier stages within the power amplifier path. The predistorters set breakpoints in a predistortion curve and divide the predistortion curve into a plurality of segments. Each predistorter may be adjusted to change the slope of each segment. This adjustment forms a piecewise curve-fit to approximate the inverse of the amplifier transfer characteristic. The curve-fit can be made arbitrarily close to the amplifier transfer characteristic by the selection of a sufficient number of breakpoints and therefore a sufficient number of predistortion curve segments, leading to a satisfactory linearization of the power amplifier.

Abstract: A distortion cancellation amplifier is described having a main amplifier and an error amplifier. The main amplifier, in response to an input signal, generates an output signal having an amplified signal component and a distortion signal component. The error amplifier is sized and biased to generate, in response to the same input signal, a distortion signal component that has substantially the same magnitude as the distortion signal component of the main amplifier. The distortion signal component from the error amplifier is subtracted from the output signal of the main amplifier.

Abstract: A variable gain amplifier is disclosed where the gain of the amplifier is controlled by a variable emitter resistor that is responsive to a control signal. The variable resistor includes a resistor connected between the collector and emitter of a control transistor. A control signal applied to the base of the control transistor varies the gain of the amplifier from a minimum gain when the control transistor is cut-off to a maximum gain when the control transistor is saturated.