Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.

Abstract: Radio frequency (RF) isolators are described, coupling circuit domains operating at different voltages. The RF isolator may include a transmitter which emits a directional signal toward a receiver. Layers of materials having different dielectric constants may be arranged to confine the emission along a path to the receiver. The emitter may be an antenna having an aperture facing the receiver.

Abstract: A transformer based digital isolator is provided that has improved immunity to common mode interference. The improved immunity is provided by placing the transformer in association with an H-bridge drive circuit, and taking additional effort to tailor the on state resistance of the transistors to control a common mode voltage at the transformer.

Abstract: A method of trimming a component is provided in which the component is protected from oxidation or changes in stress after trimming. As part of the method, a protective glass cover is bonded to the surface of a semiconductor substrate prior to trimming (e.g., laser trimming) of a component. This can protect the component from oxidation after trimming, which may change its value or a parameter of the component. It can also protect the component from changes in stress acting on it or on the die adjacent it during packaging, which may also change a value or parameter of the component.

Abstract: According to some aspects, a power regulation system for energy harvesters that lacks a battery is provided. In some embodiments, the power regulation system may receive power from multiple energy harvesters that generate energy from different sources, such as wind currents and ambient light. In these embodiments, the power regulation system may selectively provide power from one or more of the energy harvesters to a load as environmental conditions change and power itself with energy from the energy harvesters. Thereby, the power regulation system may start and operate without a battery and provide power to the load over a wider range of environmental conditions.

Abstract: Provided herein are apparatus and methods for high linearity voltage variable attenuators (VVAs). In certain configurations, a high linearity VVA includes multiple shunt arms or circuits that operate in parallel with one another between a signal node and a first DC voltage, such as ground. Thus, the shunt arms are in shunt with respect to a signal path of the VVA. The multiple shunt arms include a first shunt arm of one or more n-type field effect transistor (NFETs) and a second shunt arm of one or more p-type field effect transistor (PFETs). The gates of the NFETs are controlled using a control voltage, and the gates of the PFETs are controlled using a complementary control voltage that changes inversely with respect to the control voltage.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: A bus driver is provided that can withstand over voltages being applied to its output terminal without the protection circuit detracting from the voltage swing that can be provided by the driver. The circuit arrangement also allows transistors having good on state resistance and large tolerance of drain-to-source voltages to be used.

Abstract: A power converter can include an electrical isolation circuit between input and output nodes. An input signal monitor node can be provided, such as on a converter output side of the isolation circuit. In an example, a peak detection circuit can be coupled to the input signal monitor node. The output node of the power converter can be configured to supply an output power signal that is a function of an input signal at the input node. The power converter can include multiple, independently-switchable switches at one or more of the input and output sides of the isolation circuit. In an example, the power converter with the input signal monitor node can be configured as a bias supply to provide power, at the output node, to a controller circuit for a main stage power converter circuit.

Abstract: A delta-Vbe based bandgap reference voltage circuit generates a temperature stable reference voltage. First and second paths of the circuit each include a respective transistor coupled in series with a resistance. The collector current density of the transistor in first path is lower than the collector current density of transistor in the other path. A control path is used to generate a 2Vbe voltage that is coupled to the base nodes of the resistors in each path. A resistance that is coupled between a common node of a first end of the two paths and a circuit ground node. The circuit current is controlled by this resistance and a voltage drop of 2?Vbe is across the resistance. The output reference voltage of the circuit is 2(Vbe+?Vbe) when stack resistors in each path are used.

Abstract: A switched capacitor voltage converter is provided that includes an array of switches configured to alternately switch multiple capacitors between a charge configuration in which the multiple capacitors are coupled in series with each other and in parallel with the source voltage and a discharge configuration in which a first set of capacitors having n capacitors are coupled in parallel with each other and in series with the load and a second set of capacitors having m capacitors coupled in parallel with the load.

Abstract: A control circuit for use with a four terminal sensor, such as a glucose sensor. The Glucose sensor is a volume product and typically its manufacture will want to make it as inexpensively as possible. This may give rise to variable impedances surrounding the active cell of the sensor. Typically the sensor has first and second drive terminals and first and second measurement terminals, so as to help overcome the impedance problem. The control circuit is arranged to drive at least one of the first and second drive terminals with an excitation signal, and control the excitation signal such that a voltage difference between the first and second measurement terminals is within a target range of voltages. To allow the control circuit to work with a variety of measurement cell types the control circuit further comprises voltage level shifters for adjusting a voltage at one or both of the drive terminals, or for adjusting a voltage received from one or both of the measurement terminals.

Abstract: A transformer based isolated bi-directional DC-DC power converter may have signals for controlling power transfer in first and second directions are derived from the same side of the transformer. The converter may include a transformer, a first switching circuit, a second switching circuit, and a controller. In a first mode, the controller controls the first and second switching circuits, and power is transferred from a first side to a second side. In a second mode, the controller controls the first and second switching circuits, and power is transferred from the second side to the first side.

Abstract: Aspects of the embodiments are directed an analog front end circuit (AFE circuit), the AFE circuit including a beamforming circuit configured to receive as an input a plurality of receiver inputs, the receiver inputs coupled to a sensor element. The beamforming circuit can include a plurality of receiver sub-circuits, each sub-circuit including a digital-to-analog converter, a low noise amplifier, and an I/Q mixer circuit element; an adder circuit element at an output of the I/Q mixer circuit element; and a multiplexer coupled to an output of the adder circuit. The AFE can be part of a current sensing device. The current sensing device can include a two-dimensional array of sensor elements.

Abstract: Digital to analog converters (DAC) are used to convert digital signals to analog values. The digital system providing data to the analog converter may be highly tasked. A DAC is provided with some in built logic to assist in reducing the load on the devices driving the DAC. The DAC may include a library of functions that it can apply to the input words to modify transitions in the analog output words. The DAC may further include a health checking system for monitoring the digital words being supplied to the DAC and raising a concern, and taking action if required, if the sequence of words is unlikely to be correct or beyond the target operating range.

Abstract: A buffer is provided where a part of the buffer is implemented in switched capacitor or other analog discrete time processing circuitry and a dynamic response characteristic, such as an effective gain or charge transfer coefficient between the input stage and an output stage is digitally controllable. This means that the buffer can be driven as if it was a system controlled by, for example a three (3) term controller, giving rise to greater, digital flexibility in tailoring the buffer's transient response.

Abstract: Analog-to-digital converters (ADCs) can be used inside ADC architectures, such as delta-sigma ADCs. The error in such internal ADCs can degrade performance. To calibrate the errors in an internal ADC, comparator offsets of the internal ADC can be estimated by computing a mean of each comparator of the internal ADC. Relative differences in the computed means serves as estimates for comparator offsets. If signal paths in the internal ADC are shuffled, the estimation of comparator offsets can be performed in the background without interrupting normal operation. Shuffling of signal paths may introduce systematic measurement errors, which can be measured and reversed to improve the estimation of comparator offsets.

Abstract: A clock generation circuit coupled to an integrator circuit uses a variable resistance that is adjusted in a transconductance bias feedback circuit. This resistance is calibrated to the reciprocal of the transconductance of the input amplifier. The product of the adjusted resistance and a capacitance in the clock generation circuit provides a time constant for the settling time of the integrator and controls a pulse width of an adaptively controlled duty cycle output clock.

Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

Abstract: An integrated circuit is provided in which a surge protector, protecting against modest over-voltage events which may contain a lot of energy, and an electrostatic discharge (ESD) protector, protecting against high voltage events that may contain only a little energy, are provided within the integrated circuit package. The two types of protectors may protect against different types of electrical events.