Abstract: A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.

Abstract: Apparatus and methods for asynchronous clock mapping are provided herein. In certain configurations, an upstream server of a transport network generates clock difference data indicating a time difference between a server clock signal and a client clock signal, which have an asynchronous timing relationship with respect to one another. The clock difference data is generated with high precision by using one or more time-to-digital converters (TDCs). The clock difference data is included in a transmitted data stream, and is used by a downstream server to recover client information with enhanced accuracy.

Abstract: Aspects of this disclosure relate to a receiver for digital predistortion (DPD). The receiver includes an analog-to-digital converter (ADC) having a sampling rate that is lower than a signal bandwidth of an output of a circuit having an input that is predistorted by DPD. DPD can be updated based on feedback from the receiver. According to certain embodiments, the receiver can be a narrowband receiver configured to observe sub-bands of the signal bandwidth. In some other embodiments, the receiver can include a sub-Nyquist ADC.

Abstract: Microelectromechanical systems (MEMS) switches are described. The MEMS switches can be actively opened and closed. The switch can include a beam coupled to an anchor on a substrate by one or more hinges. The beam, the hinges and the anchor may be made of the same material in some configurations. The switch can include electrodes, disposed on a surface of the substrate, for electrically controlling the orientation of the beam. The hinges may be thinner than the beam, resulting in the hinges being more flexible than the beam. In some configurations, the hinges are located within an opening in the beam. The hinges may extend in the same direction of the axis of rotation of the beam and/or in a direction perpendicular to the axis of rotation of the beam.

Abstract: For small cells, transceivers demand high performance while maintaining system efficiency. The present disclosure describes a highly integrated cellular transceiver that offers such features by providing one or more digital functions on-chip, onto the same die in the cellular transceiver. Effectively, the scope and boundary of the cellular transceiver is expanded to move beyond the data converters of the transceiver to include a variety of digital functions, thus integrating more of the signal chain in the cellular transceiver. Integration can greatly reduce complexity for the baseband processing, lower the cost of the overall transceiver system, reduce power consumption, and at the same time, benefit from improvements on the digital functions through integration.

Abstract: Provided herein are oscillator paths between an oscillator and mixers. In an embodiment, the oscillator paths include a first path between an oscillator and a first mixer and a second path between the oscillator and the second mixer, in which the first path is enabled in a first state (e.g., a low band state) and the second path is enabled in a second state (e.g., a high band state). The first path can include a radio frequency divider configured to receive a signal having the oscillator frequency and to divide the signal in frequency by a positive odd integer divisor greater than one, and a duty cycle correction circuit configured to receive an output from the radio frequency divider and provide an output having a duty cycle that is closer to 50% than the output from the divider. Such separate oscillator paths can, for example, enhance receiver performance.

Abstract: Apparatus and methods for generating a uniform magnetic field are provided herein. In certain configurations, a magnetic structure includes one or more pairs of magnets positioned within a housing. The magnets of each pair are arranged in parallel and include poles that are reversed in polarity relative to one another. For example, in certain implementations, a first pair of magnets includes a first magnet and a second magnet arranged side by side, with a north pole of the first magnet adjacent a south pole of the second magnet and with a south pole of the first magnet adjacent a north pole of the second magnet. The housing is implemented using a magnetic redirecting material, which can confine magnetic flux and reduce stray magnetic fields. The magnetic structure can be used to generate a magnetic field that is substantially uniform in a region of interest.

Abstract: A headset driver circuit is described which comprises a connector interface. The connector interface comprises a first terminal, a second terminal and a third terminal for establishing respective electrical connections to a first speaker, a microphone and a common ground node of a headphone, earphone or headset, respectively. A first power amplifier is coupled to the first terminal to supply a first audio output signal to the first speaker of the headset. A first switch arrangement comprises a first ground switch is configured for selectively connecting and disconnecting the second terminal and a ground node of the headset driver circuit. The headset driver circuit further comprises a second ground switch configured for selectively connecting and disconnecting the third terminal and the ground node. The headset driver circuit also comprises a differential preamplifier, e.g.

Abstract: An active antenna test system is described. The active antenna test system comprises an active antenna unit comprising: a plurality of antenna elements; at least one processor; a plurality of transceiver modules operably coupled to the at least one processor and arranged to receive at least one first baseband signal for transmission via at least one of the plurality of antenna elements and arranged to pass at least one second baseband signal thereto received and down-converted from at least one of the plurality of antenna elements; and at least one switching module operably coupling the plurality of antenna modules to the plurality of transceiver modules. The active antenna test system also comprises at least one communication test equipment, such as a radio frequency, RF, test module and at least one baseband processor.

Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

Abstract: An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.

Abstract: A amplifier system may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The power amplifier may produce a distortion signal at a first frequency, the second converter may sample the output signal using a timing signal with a second frequency that is lower than the first frequency to generate the feedback signal, and the predistorter, based upon the feedback signal, may predistort the predistortion signal to reduce the distortion signal at the first frequency.

Abstract: This application provides methods and apparatus for controlling aspects of a synchronous rectifier power converter. In an example, an apparatus can include a minimum duty cycle control circuit configured to receive first control signals for one or more switches associated with the synchronous rectifier power converter, to compare a duty cycle of the first control signals to a minimum duty cycle threshold, and to provide second control signals having at least the minimum duty cycle for an active snubber switch of the synchronous rectifier power converter.

Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.

Abstract: A regulator circuit can include a cascaded topology, comprising a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node, and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and configured to provide a regulated second output voltage to an output node, where the second loop bandwidth is narrower than the first loop bandwidth. The regulator circuit need not require an external capacitor. The regulator circuit can be used to provide one or more of enhanced power supply rejection and noise performance.

Abstract: A system is described for forming an estimate of an unwanted signal component that may be formed as a result of non-linearities in a system. The estimate is used to form a cancellation signal which is added to an input signal to reduce the influence of the unwanted component.

Abstract: An oscillator for a signal isolator system includes a capacitor and an inductor connected in parallel, two pairs of cross-coupled switches and a control switch. The capacitor, the inductor and the cross-coupled switches form an oscillator. The control switch controls operation of the oscillator between an ON state and an OFF state in response to a data signal to be communicated across an isolation barrier. The inductor may be formed from a winding of an isolation transformer, which reduces component count as compared to a system that provides a separate inductor. Other embodiments may include a current-supplying kickstart circuit and a shorting transistor that can speed transition between the ON and OFF states.

Abstract: Otherwise incompatible digital predistortion and uptilt can be used together, such as in a cable television or other cable communications system having a frequency-dependent signal loss at high frequencies. The predistortion can be used to compensate for a nonlinear gain compression of a power amplifier at higher frequencies. Additional uptilt and equalizer circuits can be included to address deleterious distortion effects that may otherwise arise by using predistortion and uptilt together. Training and adaptation of various components are described. Fine and coarse uptilt adjustments can be provided.

Abstract: A timer circuit is provided comprising: a resistor; a programmable gain circuit coupled to amplify the reference level based upon a resistor and a selected gain; a detection circuit coupled to identify the amplified reference level based upon a resistor; a selection circuit configured to select the gain based at least in part upon the identified amplified reference level based upon a resistor; a comparator circuit configured to transition between providing a signal having a first value and providing a signal having a second value based at least in part upon comparisons of a reactive circuit element excitation level with the amplified reference level based upon a resistor and with a second reference level; and reactive circuit element excitation circuit configured to reverse excitation of the reactive circuit element in response to the comparator circuit transitioning between providing the signal having the first value and providing the signal having the second value.

Abstract: A MEMS apparatus has a substrate, an input node, an output node, and a MEMS switch between the input node and the output node. The switch selectively connects the input node and the output node, which are electrically isolated when the switch is open. The apparatus also has an input doped region in the substrate and an output doped region in the substrate. The input doped region and output doped region are electrically isolated through the substrate—i.e., the resistance between them inhibits non-negligible current flows between the two doped regions. The input doped region forms an input capacitance with the input node, while the output doped region forms an output capacitance with the output node.