Abstract: A negative current protection system for a low side switching converter FET, for use with a switching converter arranged to operate high and low side FETs connected to an output inductor to produce an output voltage. The negative current protection system includes a current sensing circuit which produces an output Vcs that varies with the current in the high side FET, a negative current threshold generator which produces a threshold signal ?Ith which represents the maximum negative current to which the low side FET is to be subjected, and a comparison circuit arranged to compare the valley portion of Vcs and -Ith and to set a flag if Vcs<?Ith at a predetermined time in the switching cycle—typically after the converter's blanking time. When the flag is set, the system preferably responds by adjusting the operation of the switching FETs to reduce the negative current.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p?p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p?p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract: A switching power converter includes a voltage source that provides an input voltage Vin to an unregulated DC/DC converter stage and at least one buck-boost converter stage to produce a desired output voltage Vout. The unregulated DC/DC converter stage is adapted to provide an isolated voltage to the at least one regulated buck-boost converter stage, wherein the unregulated DC/DC converter stage comprises a transformer having a primary winding and at least one secondary winding and at least one switching element coupled to the primary winding. The at least one buck-boost converter stage is arranged to operate in a buck mode, boost mode or buck-boost mode in response to a mode selection signal from a mode selection module. By influencing the pulse width modulation output power controller the at least one buck-boost converter stage is arranged to produce one or multiple output voltages.

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by denormalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value.

Abstract: An amplifier may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The predistorter may separately and independently generate a predistortion signal component for the in-phase input signal and a predistortion signal component for the quadrature input signal.

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract: An amplifier system may include a power stage having inputs for three different supply voltages and an output for coupling to a load, a controller to generate control signals to the power stage that cause the power stage to vary an output voltage applied to the load among more than three distinct voltage levels, a monitor to provide a first control signal to the controller based on an input voltage signal, and a feedback system to provide a second control signal to the controller based on comparison of the output voltage and the input signal.

Abstract: The present disclosure proposes a fully integrated accurate LED output current controlling circuit and method, which can be seamlessly combined with true PWM dimming. The current controlling circuit has an auto zero function in the light-emitting diode driver to eliminate offsets caused by the system, process variations, parasitic effects, dimming and so on in an LED driver application, and thus is capable of controlling the LED current with high accuracy. Moreover, the driver of the present disclosure does not require the use of external components such as an external resistor to regulate current accuracy.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Abstract: A root-mean-square (RMS) detector includes detection circuitry having as an input a radio frequency signal, target voltage and a set voltage and a RMS signal as an output, and a gain stage within the detection circuitry to produce the RMS signal as an output. The gain stage provides for faster settling times of the detector.