Abstract: A low drop out voltage regulator comprising: a transistor having an input node, an output node, and a control node; a differential amplifier having an output connected to the control node of the transistor and having a first input node; and a feedback capacitor connected between the output node of the transistor and the first input of the differential amplifier, wherein a voltage at the output of the transistor is dependent on a charge across the feedback capacitor.

Abstract: A duty cycle balance module (DCBM) for use with a switch mode power converter. One possible half-bridge converter embodiment includes a transformer driven to conduct current in first and second directions by first and second signals during and second half-cycles, respectively. A current limiting mechanism adjusts the duty cycles of the first and second signals when a sensed current exceeds a predetermined limit threshold. The DCBM receives signals representative of the duty cycles which would be used if there were no modification by the current limiting mechanism and signals Dact—1 and Dact—2 representative of the duty cycles that are actually used for the first and second signals, and outputs signals Dbl—1 and Dbl—2 which modify signals Dact—1 and Dact—2 as needed to dynamically balance the duty cycles of the first and second signals and thereby reduce flux imbalance in the transformer that might otherwise arise.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the DAC comprises a first and second switching network, the second switching network providing multiple switched paths which compensate for impedance effects of the second string and provides multiple state changes at the output node of the DAC.

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract: A circuit may include a splitter, a controller, and a termination. The splitter may generate, based upon input signals, a plurality of output signals, wherein at least one of the input signals is in more than one different modes at different times and the output signals comprise a first set of the output signals generated based upon comparison of pairs of signals of the first set against each other and a second set of the output signals generated based upon comparison of each signal of the second set to a predetermined threshold voltage. The controller may determine, based upon the second set of the output signals, whether the input signals are in the one of the more than one different modes to generate one or more control signals. The termination may connect loads to each of the input lines, based upon the one or more control signals.

Abstract: A miniature loudspeaker may include a driver module with a flexible carrier having a proximal portion arranged within the perimeter of the frame and a distal portion arranged outside the perimeter of the frame, the flexible carrier carrying an output amplifier. The flexible carrier may be provided with electrically conductive traces connecting an amplifier input with input contact pads placed on the distal portion. The flexible carrier may be provided with electrically conductive traces connecting an amplifier output with output contact pads placed at the proximal portion. The output amplifier may be arranged on the proximal portion of the flexible carrier within the perimeter of the frame. The proximal portion of the flexible carrier may be rigidly attached to the static part. The output contact pads may be connected with the voice coil through flexible lead wires.

Abstract: In a multi transmitter-receiver system, transmitter noise cancellation may be applied selectively for certain transmitters by exploiting asymmetries of the system. Hence, observation receiver(s) numbering less than the number of transmitters may be provided saving space and cost. Each observation receiver may selectively couple to a transmitter path and estimate the leakage noise from that transmitter. Based on the estimated leakage noise, noise cancellation may be applied to corresponding receiver path(s). Selection of the transmitters for leakage estimation may be based on system conditions at that time, which may be known to the system or may be estimated dynamically.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. A control loop is provided to control the Ron of the switching network and provide code dependent control of switches in a DAC switching network.

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by decimalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value.

Abstract: Embodiments of the present invention may include power amplifier architectures and systems for use in wireless communication systems. The systems may include a first circuit path for receiving an input signal and decomposing the signal into two vector signals using an out-phasing generator, modifying the vectors based on predetermined value limit, amplifying the vectors using power amplifiers, and combining the vectors to provide an amplified output. The system may include a second circuit path for generating an estimate of an envelope of the input signal and using the envelope to modulate the voltage supplies of the power amplifiers when amplifying the vector signals. The system may also include a feedback path for sending information regarding the envelope of the input signal into the out-phasing generator, which may modify the vector signals in response thereto.

Abstract: In an example, a multistring DAC is described and includes at least two DAC stages. Each DAC stage includes a string of impedance elements and a switching network. In one configuration, the multi-string DAC is configured to use the voltage change at terminals of a first string separately to the voltage drop across a first switching network that couples the first and second strings to provide an analog output in response to a digital input to the DAC.

Abstract: A circuit may include a plurality of primary digital-to-analog (DAC) elements for converting a digital input signal into an analog output signal. A control circuit may control each primary DAC element to switch between a first state and a second state based on the digital input signal to provide the analog output signal at an output representing the digital input signal. A plurality of corrective DAC elements may be coupled in parallel to the plurality of primary DAC elements between the control circuit and the output. The plurality of corrective DAC elements may be controlled to mitigate for intersymbol interference (ISI) due to parasitic capacitance in the primary DAC elements. The plurality of corrective DAC elements may not contribute a direct current to the analog output signal.

Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.

Abstract: An inductor current emulation circuit for use with a switching converter in which regulating the output voltage includes comparing an output which varies with the difference between the output voltage and a reference voltage with a ‘ramp’ signal which emulates the current in the output inductor. A current sensing circuit produces an output which varies with the current in the switching element that is turned on during the ‘off’ time, an emulated current generator circuit produces the ‘ramp’ signal during both ‘off’ and ‘on’ times, a comparator circuit compares the ‘ramp’ signal with at least one threshold voltage which varies with the sensed current and toggles an output when the ‘ramp’ exceeds the thresholds, and a feedback circuit produces an output which adjusts the ‘ramp’ signal each time the comparator circuit output toggles until the ‘ramp’ signal no longer exceeds the threshold voltages.

Abstract: In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.

Abstract: A digital-to-analog conversion system includes a digital-to-analog converter and an output stage for converting an output signal of the digital-to-analog converter into a voltage range. The output stage includes a first amplifier including a first input for receiving the output signal of the digital-to-analog converter, a first resistance element coupled between a second input and an output of the first amplifier, a second resistance element coupled between the second input of the first amplifier and a ground reference, and a third resistance element switchably coupled from the second input of the first amplifier to an offset voltage.

Abstract: Embodiments of the present disclosure may provide a relaxation oscillator with improved performance against phase noise error. The phase noise error may be reduced from sources whose power is greater at lower frequencies. To reduce the noise error, the relaxation oscillator may include chopping in the charging current driver; chopping in the trigger level generator; and/or chopping in the currents that feed the cells. A chopped amplifier may be provided to perform chopping of the input signals.

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract: An all digital model of nonlinear transmitter signal distortion in signals received at a receiver of a transmitter-receiver may be used to estimate distortion. The estimated distortion may then be cancelled from the received signals to improve signal quality of the received signal. The digital nonlinear model may be part of an estimator circuit that estimates nonlinear distortion terms by applying a formula or transformation to a digitized version of the signals transmitter at a transmitter of the transmitter-receiver. A mixer may be used to shift a frequency of the estimated nonlinear terms away from a transmitter frequency so that the nonlinear terms can later be subtracted from the incoming signal received at the receiver at a receiver frequency. Circuits and methods are provided.

Abstract: Apparatus and methods for current sensing in switching regulators are provided. In certain implementations, a switching regulator includes a switch transistor, a replica transistor, a current source, a sense resistor, and a current sensing circuit. The drain and gate of the switch transistor can be electrically connected to the drain and gate of the replica transistor, respectively. Additionally, the current sensing circuit can control the voltage of the source of the replica transistor based on the polarity of a current through the switch transistor to generate an output current that changes in response to the switch transistor's current. The sense resistor can receive an offset current from the first current source and the output current from the current sensing circuit such that the voltage across the sense resistor changes in relation to the current through the switch transistor.