Abstract: An exemplary object detection method includes generating feature block components representing an image frame, and analyzing the image frame using the feature block components. For each feature block row of the image frame, feature block components associated with the feature block row are evaluated to determine a partial vector dot product for detector windows that overlap a portion of the image frame including the feature block row, such that each detector window has an associated group of partial vector dot products. The method can include determining a vector dot product associated with each detector window based on the associated group of partial vector dot products, and classifying an image frame portion corresponding with each detector window as an object or non-object based on the vector dot product. Each feature block component can be moved from external memory to internal memory once implementing the exemplary object detection method.

Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.

Abstract: A method includes determining a position and length of a non-zero run in a row of a pixel map. The method also includes determining a number of neighbors for the non-zero run in a preceding row, based at least in part on the position and the length. In addition, the method includes updating a correspondence map of the non-zero run and a correspondence map of a first neighbor of the non-zero run, based at least in part on a correspondence map of a second neighbor of the non-zero run, in response to a determination that the non-zero run has at least two neighbors in the preceding row.

Abstract: A power converter may include an amplifier that generates an error signal, a modulator that generates a modulated error signal, an isolator that generates an isolated modulated error signal, and a demodulator that generates an isolated error signal, which may be substantially proportional to the difference between the output signal and the reference signal, and a controller that controls a power stage to generate the output signal of the power converter.

Abstract: A duty cycle balance module (DCBM) for use with a switch mode power converter. One possible half-bridge converter embodiment includes a transformer driven to conduct current in first and second directions by first and second signals during and second half-cycles, respectively. A current limiting mechanism adjusts the duty cycles of the first and second signals when a sensed current exceeds a predetermined limit threshold. The DCBM receives signals representative of the duty cycles which would be used if there were no modification by the current limiting mechanism and signals Dact—1 and Dact—2 representative of the duty cycles that are actually used for the first and second signals, and outputs signals Dbl—1 and Dbl—2 which modify signals Dact—1 and Dact—2 as needed to dynamically balance the duty cycles of the first and second signals and thereby reduce flux imbalance in the transformer that might otherwise arise.

Abstract: This disclosure relates to temperature stabilization of at least a portion of an amplifier, such as a logarithmic amplifier, and/or a band gap reference circuit. In one aspect, one or more stages of an amplifier, a heater, and a temperature sensor are included in a semiconductor material and surrounded by thermally insulating sidewalls.

Abstract: Aspects of this disclosure relate to a termination circuit configured to mitigate crosstalk from a radio frequency (RF) input/output (I/O) path to a second I/O path, such as a digital I/O path. Such crosstalk can be due to coupling between adjacent bond wires, for example. The termination circuit can include a low impedance loss path, such as a series RC shunt circuit. According to certain embodiments, an electrostatic discharge (ESD) protection circuit can be in parallel with the termination circuit.

Abstract: In certain applications, differential amplifiers with infinite common mode rejection ratios are desirable. However, resistance mismatches due to imperfections in the manufacturing create finite common mode rejection ratio in differential amplifiers degrading their performance. Disclosed are apparatus and method for improving the common mode rejection ratio of practical differential amplifiers.

Abstract: A method of detecting enclosure leakage of an electrodynamic loudspeaker mounted in an enclosure or box may include applying an audio signal to a voice coil of the electrodynamic loudspeaker through an output amplifier and detecting a voice coil current flowing into the voice coil. A voltage across the voice coil may be detected and an impedance or admittance of the loudspeaker across a predetermined audio frequency range may be detected based on the detected voice coil current and voice coil voltage. A fundamental resonance frequency of the loudspeaker may be determined based on the detected impedance or admittance and compared with a nominal fundamental resonance frequency of the loudspeaker representing a sealed state of the enclosure. Acoustic leakage of the enclosure may be detected based on a deviation between the determined the fundamental resonance frequency and the nominal fundamental resonance frequency of the electrodynamic loudspeaker.

Abstract: A semiconductor device having a first layer adjoining a semiconductor layer, and further comprising at least one field modification structure positioned such that, in use, a potential at the field modification structure causes an E-field vector at a region of an interface between the semiconductor and the first layer to be modified.

Abstract: Apparatus and method for acquiring and tracking a data signal are disclosed. Two different CDR circuits are configured to acquire and track data based on two different modulation schemes. While in the acquisition mode, the first CDR circuit may acquire data signal by sampling the signal at a reduced clock rate and handover to the second CDR circuit when a preamble is found. Also in the acquisition mode, the data acquisition and tracking circuit may determine the power level of the preamble signal and dynamically adjust the threshold level for the tracking period upon finding of the preamble.

Abstract: A MEMS sensor includes a micro-electromechanical structure, a detection circuit, and a self-test circuit to test the health of the MEMS sensor during runtime operations. The self-test circuit is configured to inject into the micro-electromechanical structure a plurality of injected test signals that are broad-band frequency-varying frequency signals, which are based on spread spectrum based modulation. The injected test signals may a magnitude that is below an observable threshold of the sensor signal as well as a test-signal bandwidth that overlaps with a substantial portion of the sensor bandwidth, including the stimulus of interest.

Abstract: The present disclosure provides a stream processor, an associated stream controller and compiler, and associated methods for data processing, such as image processing. In some embodiments, a method includes defining a kernel pattern associated with an image frame, and processing the image frame using the defined kernel pattern. The method can further include generating a kernel switch lookup table based on the defined kernel pattern. In various implementations, the stream controller is operable to direct execution of kernels on the image frame according to the defined kernel pattern and the kernel switch lookup table.

Abstract: An amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit.

Abstract: A switching regulator or other apparatus or techniques can include load current monitoring to provide a digital representation of an estimated load current. Load current monitoring can be performed by a circuit including a counter circuit, a comparator circuit, and a digitally-controlled source coupled to the counter circuit and configured to adjust a bias condition of a sensing device in response to a count provided by the counter circuit in order to establish a proportional relationship between a current conducted by the sensing device and a corresponding current conducted by a power switching device. The counter circuit is configured to increment and decrement the count in response to information provided by the comparator output and the count is generally indicative of the estimated load current, such as an average load current.

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by decimalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value.

Abstract: In one aspect, this disclosure relates to a method of controlling current output from a switching regulator to a load via an inductor. Inductor current information can be sampled at a peak level, such as just before a transistor configured to cause current to flow through the inductor is turned off. The sampled inductor current can be compared with a reference current, and a current limit threshold can be adjusted based on the comparison. The output current of the switching regulator can be controlled based on a comparison of the current limit threshold with an indicator of current flowing through the inductor. This method can accurately and efficiently limit current in a switching regulator.

Abstract: A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.

Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).

Abstract: An example transconductance circuit is provided in accordance with one embodiment. The transconductance circuit can comprise: an output node; at least one transistor; a variable resistance; and a differential amplifier; wherein the at least one transistor and the variable resistance are in series connection with the output node, an output of the differential amplifier is connected to a control node of the at least one transistor, a first input of the amplifier is responsive to an input signal, and a second input of the amplifier is responsive to a voltage across the variable resistance. Such a circuit may overcome noise problems in transconductance circuits which operate over a wide range of input signals with a fixed resistor in series with the at least one transistor.