Abstract: A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.

Abstract: An apparatus comprises a power converter circuit and a control circuit. The power converter circuit includes a primary circuit side and a secondary circuit side. The primary circuit side includes a plurality of primary switches, and the secondary circuit side includes a plurality of synchronous rectifiers and an inductor. The control circuit is configured to operate the synchronous rectifiers synchronously with the primary switches when inductor current at the inductor is greater than or equal to a reference inductor current, and operate the synchronous rectifiers in a bidirectional mode when the inductor current is less than the reference inductor current, wherein energy is delivered from the primary side to the secondary side and from the secondary side to the primary side during the bidirectional mode.

Abstract: A transconductance gain stage including a pair of gain transistors, each gain transistor having a base and an emitter, the emitter of each gain transistor electrically coupled to a degenerating resistor, and the emitter of each gain transistor connected to a gain resistor.

Abstract: A system for processor wake-up based on sensor data includes an audio buffer, an envelope buffer, and a processor. The audio buffer is configured to store a first data from a sensor. The first data is generated according to a first sampling rate. The envelope buffer is configured to store a second data, which is derived from the first data according to a second sampling rate, which is less than the first sampling rate. The processor is configured to wake up periodically from an idle state and read the second data from the envelope buffer. If the second data indicates an activity, the processor is configured to read the first data from the audio buffer. If the second data does not indicate an activity, the processor is configured to return to the idle state.

Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract: A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance.

Abstract: Present disclosure describes an improved mechanism for addressing component mismatch in a DAC. The mechanism is based on carefully selecting the first DAC unit of an ordered sequence of DAC units that are switched on to convert a particular digital value to an analog value. The mechanism benefits from recognition that selecting the first DAC based on a value of a band-limited dither signal, where the band of the dither signal is selected to be sufficiently removed from the band of the signal of interest, allows shifting effects of DAC units mismatch away from the signal of interest in a manner that is easy to implement and control. Because dither signal is not added to the signal of interest, but is only used to control which DAC units are turned on, drawbacks of a traditional dithering method can be avoided while benefiting from the use of dither.

Abstract: Early effects are intrinsically present in bipolar junction transistors (BJTs). Described are examples of complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) cells that reduce errors associated with the Early effects that would otherwise be present.

Abstract: Embodiments of full duplex radios are disclosed herein. For example, a radio may include: a first transmitter, a second transmitter, and a receiver. The first transmitter may be configured to receive an input signal, process the input signal to generate a first transmit signal, and transmit the first transmit signal. The second transmitter may be configured to receive the input signal, process the input signal to generate a second transmit signal, and couple the second transmit signal into an input path of the receiver. Leakage at the receiver may thus be reduced. Some embodiments of a radio may also include a base band correction circuit and means for reducing transmitter noise that leaks into the receiver.

Abstract: In contrast to some existing techniques, a calibration technique compares multiple outputs which may be, for example, successive or different outputs from the digital-to-analog converter (DAC) in an analog environment and determines differences between at least two outputs in an analog environment. A feedback signal is provided in the digital environment to provide an internal or self-calibration regime. The digital feedback signal is provided to a digital signal processing (DSP) component of the calibration circuitry which uses the feedback signal to determine appropriate input codes to provide to the DAC. The same DAC can be used for both signal generation and feedback DAC purposes, and this provides a self-calibration of the DAC performance which is typically related to the integral non-linearity (INL) characteristics of the DAC transfer function.

Abstract: A proportional to absolute temperature, PTAT, circuit is provided. By judiciously combining circuit elements it is possible to generate a voltage at an output node of the circuit that is temperature dependent. Such a PTAT circuit can be used as a temperature sensor or can be combined with other temperature dependent circuits to provide a voltage reference.

Abstract: The present invention relates to current measurement apparatus 100. The current measurement apparatus 100 comprises a measurement arrangement 110, 114 which is configured to be disposed in relation to a load 108 which draws a current signal, the measurement arrangement being operative when so disposed to measure the load drawn current signal. The current measurement apparatus 100 also comprises a signal source 112 which is operative to apply a reference input signal to the measurement arrangement 110, 114 whereby an output signal from the measurement arrangement comprises a load output signal corresponding to the load drawn current signal and a reference output signal corresponding to the reference input signal.

Abstract: An amplifier input stage comprising first and second p-type transistors, wherein sources of the first and second p-type transistors are connected to a first node, a drain of the first p-type transistor is connected to a first output of the amplifier input stage, a drain of the second p-type transistor is connected to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal; first and second n-type transistors, wherein sources of the first and second n-type transistors are connected to a second node, a drain of the first n-type transistor is connected to a third output of the amplifier input stage, a drain of the second n-type transistor is connected to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first sign

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (??) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

Abstract: Apparatus and methods for dual loop power amplifier digital pre-distortion systems are disclosed. In certain implementations, a dual DPD system includes a first digital pre-distorter (DPD) and a second DPD. A digital IF upconverter electrically coupled between the first and second DPDs separates the DPD system into independently controlled fine and coarse sections. The adaptive adjustment processor can be used to modify or pre-distort input signals in order to compensate for the power amplifier nonlinearity. It also controls the fine DPD section to correct an RF output signal single-band adjacent channel leakage ratio (ACLR), while it controls the coarse DPD section to correct an RF output signal dual band intermodulation distortion (IMD).

Abstract: An apparatus comprises an output port for a circuit load, a first input port for an energy harvest source, an input/output port a second energy source, a first circuit path from the energy harvest source to the second energy source at the input/output port and to the variable load at the output port, a second circuit path from the second energy source to the output port, a cold start circuit that produces a first voltage level at the output port by charging a capacitor at the output port using energy of the energy harvest source, and a main converter circuit that produces a second regulated voltage level at the input/output port using energy of the energy harvest source when the voltage at the output port capacitor is above a specified voltage value and uses the energy of the capacitor at the output port during startup of the main converter circuit.

Abstract: In an example embodiment, an amplifier having high gain and high slew rate is provided and includes a pair of input transistors to which input voltage is applied, a pair of diode-connected loads coupled to the input transistors, at least one pair of current sources coupled to the diode-connected loads, and a bias control configured to turn off the at least one pair of current sources to enable high slew rate for the amplifier and to turn on the at least one pair of current sources to enable high gain for the amplifier. In specific embodiments, the current sources include transistors, the bias control controls a bias voltage to the current sources, and the bias voltage is driven to the supply voltage (VDD) to turn off the current sources.

Abstract: A Segmented Voltage Continuous-Time Digital-to-Analog Converter is disclosed which provides the benefits of segmentation while minimizing the associated disadvantages. The segmented digital to analog converter disclosed here features, in particular, inherent monotonicity and low transition glitches. The segmentation technique is based on coupling an array of switchable current sources and at least one current divider into a resistor string, providing, at least, three levels of segmentation.

Abstract: Physical layouts of ratioed circuit elements, such as transistors, are disclosed. Such layouts can maintain electrical characteristics of the ratioed circuit elements relative to one another in the presence of mechanical stresses applied to an integrated circuit, such as an integrated circuit encapsulated in plastic. The ratioed circuit elements can include first and second composite circuit elements formed of first and second groups of circuit elements, respectively, arranged around a center point. The first group of circuit elements can be arranged on a grid and the second group of circuit elements can include four circuit elements spaced approximately the same distance from the center point. Each of the circuit elements in the second group can be off the grid in at least one dimension. The first and second groups of circuit elements can be arranged around a perimeter of dummy circuit elements in some embodiments.