Abstract: Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit.

Abstract: According to various aspects, systems and methods are provided for secure communication between a passive sensor node and a reader. A passive sensor node may be used for monitoring in a variety of situations. A reader may power the passive sensor while communicating with the passive sensor. In some scenarios, it may be necessary or desirable to provide security between the passive sensor and the reader. According to one aspect, the reader may send a first message initiating communication with the passive sensor, which may respond with a second message including encrypted data. An authorized reader may decrypt the data and respond with data encrypted based on the second message in a third message, which may be used by the device to authenticate the reader.

Abstract: System and apparatus for pulse oximetry. Systems, methods, and devices are presented for placement of the hardware on a body part where detracting signals are strong. In one example, detracting signals include signals from respiration. In various examples, the body part the oximeter is placed on is a wrist, chest, or arm. A computationally efficient pipeline is presented that allows for reliable and robust SpO2 estimation.

Abstract: A deskew system can be used to adjust signal characteristics such as pulse width and edge timing. In an example, a deskew system can include multiple timing control cells and each cell can operate in one of multiple different modes according to respective mode control signals. The modes can include at least a signal delay mode and a signal pulse width adjustment mode. In an example, a first cell in a deskew system can be configured to receive a test input signal at a first input node and, in response, provide a deskew output signal at a first output node. The deskew output signal can be based on the test input signal, a pulse width adjustment provided by the first cell, and on a delayed signal, corresponding to the input signal, that is provided by a subsequent cell in the series.

Abstract: A method and electronic device for configuring a PUF, wherein: PUF cells are configured to use a signal path; determining a winner of racing pairs of PUF cells in a first round and in a second round wherein winners of the first round are raced; the first and second round are repeated for different signal paths; determining, for each signal path, a comparison metric, wherein the comparison metric is based on the count of the outputs of the PUF cells having the signal path in common; determining an optimum signal path for the PUF from the respective comparison metrics; and configuring the PUF to use the optimum signal path.

Abstract: A device for proximity detection includes multiple electrodes and an impedance sensor coupled to the electrodes. The impedance sensor may include three impedance elements and a sensing element arranged in a bridge configuration to offset an external impedance and detect changes to impedance in the environment of the device. The device further includes a proximity detector that obtains sensor measurements between multiple subsets of electrodes and analyzes the sensor measurements to determine whether an object is approaching the device.

Abstract: Apparatus and methods for controlling a clock signal are provided. In certain embodiments, a semiconductor die includes a core circuit and a clock interface circuit that provides a clock signal to the core circuit. The clock interface circuit includes an oscillator for generating an oscillator signal, and a comparator for controlling operation of the clock interface circuit in a selected clock control mode based on comparing an electrical characteristic of the clock interface pin to a comparison threshold. The selected clock control mode is chosen from a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on a clock interface pin, or a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal.

Abstract: Amplifiers can be found in pipelined ADCs and pipelined-SAR ADCs as inter-stage amplifiers. The amplifiers can in some cases implement and provide gains in high speed track and hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and samplers of high speed ADCs. The amplifiers can be employed without resetting, and with incomplete settling, to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.

Abstract: Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.

Abstract: Embodiments of the present disclosure relate to cellular technology applications of beamforming performed in the digital domain. In one aspect, an RF system for performing digital beamforming on a per-carrier basis is disclosed, where different phase and/or amplitude adjustments are applied to signals of different frequency ranges (i.e., to different carrier signals). In another aspect, an RF system for performing digital beamforming on a per-antenna basis is disclosed, where different phase and/or amplitude adjustments are applied to signals transmitted from or received by different antennas. In some embodiments, an RF system may be configured to implement both digital beamforming on a per-carrier basis and digital beamforming on a per-antenna basis. The RF systems disclosed herein allow implementing programmable beamforming in the digital domain in a manner that is significantly less complex than conventional implementations.

Abstract: An impedance sensing circuit includes three impedance elements and a sensing element arranged in a bridge configuration. A first input terminal is coupled to two of the impedance elements to apply a stimulus signal. In a mutual-sensing mode, a second input terminal is coupled to the third impedance element and the sensing impedance element to apply an opposite phase stimulus signal. The impedance sensing circuit may be configured in a self-sensing mode, in which the opposite phase stimulus signal is decoupled from the third impedance element and the sensing impedance element. At least one of the impedance elements is variable and may be adjusted to balance an offset impedance load on the sensing element.

Abstract: An exponential scale pulse width modulation (PWM) controller comprises a waveform generator circuit configured to generate a logarithmic waveform signal that has the shape of an increasing logarithm function; and a first comparator circuit including a first input to receive the logarithmic waveform signal, a second input to receive an input signal, and an output that provides a PWM control signal that includes signal pulses having a duty cycle that changes exponentially with respect to the input signal.

Abstract: An integrated circuit (IC) die is disclosed. The IC die can include a signal via extending through the IC die. The IC die can include a transmission line extending laterally within the IC die in a direction non-parallel to the signal via, the transmission line configured to transfer an electrical signal to the signal via. The IC die can include a matching circuit disposed between the transmission line and the signal via. The matching circuit can include inductance and capacitance matching circuitry to compensate for parasitic inductance and capacitance introduced by transition from the IC die to an underlying carrier.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: An image processing system having on-the-fly calibration uses the placement of the imaging sensor and the light source for calibration. The placement of the imaging sensor and light source with respect to each other affect the amount of signal received by a pixel as a function of distance to a selected object. For example, an obstruction can block the light emitter, and as the obstruction is positioned an increasing distance away from the light emitter, the signal level increases as light rays leave the light emitters, bounce off the obstruction and are received by the imaging sensor. The system includes a light source configured to emit light, and an image sensor to collect incoming signals including reflected light, and a processor to determine a distance measurement at each of the pixels and calibrate the system.

Abstract: The present disclosure enables firmware-based interleaved-ADC gain calibration and provides hardware-thresholding enhancements. An on-chip memory may store subADC samples and a microprocessor accesses these stored samples for use with the calibration algorithm. Power estimates may be performed using square of each subADC sample to estimate gain error. Thresholding may be applied to the subADC samples, such as Maximum Amplitude Thresholding, Minimum Power Thresholding, and/or using Histogram Output Memory, to determine that samples are valid and may be used for calibration or that subADC data are to be discarded and a new subADC data capture is to be started.

Abstract: Single-axis teeter-totter accelerometers having a plurality of anchors are disclosed. The plurality of anchors may be arranged about a rotation axis of the teeter-totter proof mass. Each of the plurality of anchors may be coupled to the proof mass by two torsional springs each extending along the rotation axis. The plurality of anchors allows an increased number of torsional springs to be coupled to the proof mass and thus greater torsional stiffness for the proof mass may be achieved. Due to the higher torsional stiffness, the disclosed single-axis teeter-totter accelerometers may be deployed in high-frequency environments where such increased torsional stiffness is required, for example, around 20 kHz and above.

Abstract: An integrated circuit (IC) die having a first side and a second side opposite the first side is disclosed. The IC die can include a signal via through the IC die. The IC die can include processing circuitry. The IC die can include transition circuitry providing electrical communication between the processing circuitry and the signal via. The transition circuitry can comprise a first transmission line, a second transmission line, and a transition transmission line between the first and second transmission lines. In various embodiments, the first transmission line can comprise a microstrip (MS) line, and the second transmission line can comprise a grounded coplanar waveguide (CPW).

Abstract: Disclosed herein are systems and techniques for audio and lighting control in a bus system. For example, in some embodiments, a bus system may be configured for operation as a light organ and/or to generate sound effects based on accelerometer data.