Abstract: A method and system which combines a properly designed FEC and the periodic transmission of known symbols to obtain a desired error performance in a point-to-multipoint digital transmission system employing a DFE which induces error propagation. A transmitter unit includes a forward error correction encoder (FEC) which implements a code to information provided to an input of a data interleaver having block length N and interleaving depth D, and a data modulator which is coupled to an output of the data interleaver to receive a stream of data symbols. At least one receiver unit includes a decision feedback equalizer (DFE) which includes a feedback filter and provides an input to a data deinterleaver having block length N and interleaving depth D, and a FEC decoder which receives data from an output of the data deinterleaver. Sequences of known symbols of length at least equal to the length of the feedback filter are periodically added to the output of the data interleaver.

Abstract: A biasing scheme for a multi-tanh amplifier improves the dynamic range of the amplifier by utilizing emitter degeneration resistors to reduce uncorrelated noise contributed by current source transistors used to bias the multi-tanh core. The current source transistors form part of a current mirror which can be coupled to a linear-in-dB cell through another current mirror to provide linear-in-dB gain control. An optimal version of the biasing scheme for a multi-tanh triplet minimizes noise at high gain while maximizing linearity and input signal range at low gain by varying both the absolute and relative magnitudes of the bias currents for the triplet core, thereby varying the shape of the transconductance function. The variable bias currents are provided by a multiple output current mirror in which the emitter of the center mirror transistor is connected directly to power supply ground, while the outer mirror transistors include degeneration resistors in their emitter paths.

Abstract: An analog multiplier includes a new circuit topology, which includes coupling an amplifier between the collector of one of the input transistors and the bases of the other two input transistors. The amplifier used in the new topology is a double emitter-follower. The collector currents in the other two input transistors are "forced" using the conventional topology but by a simple two transistor forcing circuit comprising a Darlington emitter-follower pair rather than the conventional operational amplifier. The simple forcing circuits allow the multiplier to be used in very low voltage applications having only a single supply voltage. Voltage to current converters can be used on the front end to convert voltage input signals to current input signals, which are then provided to the analog multiplier. The voltage to current converter uses a pre-biasing scheme to produce a linear relationship between the input voltages and the input currents across the entire voltage range of the input voltages.

Abstract: A protection circuit for an excitation current source protects against excessive compliance voltage by using a cascode transistor between the current source and an output terminal, and a transistor coupled to the output terminal and to the control lead of the cascode transistor to cause the cascode transistor to turn off if the voltage exceeds a threshold level.

Abstract: A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved by employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed, and by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation. The invention is applicable to both switching and linear voltage regulators.

Abstract: A drive circuit for an oscillator having an LC tank reduces phase noise by maximizing the oscillation amplitude and minimizing the drive to the tank. The drive circuit utilizes a capacitive attenuator network for level shifting the oscillation signal before feeding it back to the drive transistors in the drive circuit, thereby allowing a large peak voltage swing across the tank without saturating the transistors. An adaptive control circuit controls the biasing of the drive transistors and reduces the drive to the tank when the maximum oscillation amplitude is reached so that the drive circuit replenishes just the minimum amount of energy lost in the tank during each cycle, thereby minimizing the coupling of active circuit noise into the tank.

Abstract: Apparatus for detecting a tooth of a body. The tooth has an edge terminating in a notch. The tooth and notch are disposed along an edge of the body. The apparatus includes a pair of Hall effect cells disposed adjacent to, and laterally disposed along, the edge of the body. A magnet is positioned to provide a magnetic field through the edge of the body and Hall effect cells. The magnitude of field passing through the Hall effect cells is related to the relative position between the tooth and Hall effect cells. The Hall effect cells produce an output voltage related to magnitude of magnetic field passing through the cell. A differencing circuit is fed by the pair of Hall effect cell produced voltages for producing a difference signal having a peak when the edge of the tooth is positioned between the pair of Hall effect cells. A peak detector detects the peak produced by the difference signal.

Abstract: A circuit that produces a gate drive voltage for a MOS transistor switch, that receives an input voltage "on" a source terminal, includes a first input that receives the input voltage, a second input that receives a bias voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the input voltage and the bias voltage during a first of first and second non-overlapping time intervals. A second switch connects the voltage storage element to increase the sampled voltage by another of the input voltage and the bias voltage to the gate drive voltage during the second non-overlapping time interval, while maintaining the gate drive voltage less than a breakdown voltage of the MOS transistor switch. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch such that a gate-to-source voltage of the MOS transistor switch is maintained approximately constant.

Abstract: In an output stage for a DAC, such as an oversampled DAC, an apparatus and method which generates, for each bit clock period and for each bit to be converted, two or more (not just one) return-to-zero (RTZ) signals. The RTZ signals are delayed from the other (if two RTZ signals are employed, they are delayed by one-half clock cycle relative to each other). The two RTZ signals are summed to yield the DAC output from said bit.

Abstract: A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory may include first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and may include first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. A data alignment buffer is provided between the memory banks and the computation blocks. The data alignment buffer permits unaligned accesses to specified operands that are stored in different memory rows. The specified operands are supplied to one or both of the computation blocks in the same processor cycle.

Abstract: An electronic vernier realizes programmable gain steps with first and second impedance ladders, a plurality of activatable coupling networks and a switch network. The ladders receive and progressively process the differential input signal into a plurality of progressive differential signals. In an embodiment, the coupling networks each generate a respective one of a plurality of progressive differential output signals in response to a respective one of the progressive differential signals and the switch network activates any selected one of the coupling networks. Thus, any selected vernier step is obtained by activating the respective coupling network. The verniers can be integrated into various systems, e.g., programmable amplifiers.

Abstract: An isolator having a driver circuit which responsive to an input signal drives appropriate signals into one or more coils which are magnetically coupled to one or more corresponding MR or GMR elements whose resistance is variable in response to the magnetic field applied by the coil(s), and an output circuit that converts the resistance changes to an output signal corresponding to the input signal. A Faraday shield is interposed between the coil(s) and the MR or GMR elements. Common mode transients applied to the driver are capacitively coupled from the coil(s) into the Faraday shield and therethrough to ground, instead of into the MR elements. A second Faraday shield may be disposed in spaced relationship with the first Faraday shield and referenced to the potential of the MR elements for even greater common mode rejection. The entire structure may be formed monolithically as an integrated circuit on a single substrate, for low cost, small size, and low power consumption.

Abstract: A switched-gain cascode amplifier changes gain by using a differential pair of cascode transistors to switch signal current to one of two different input terminals of a loading network. The load is connected to the loading network which attenuates the output signal by a different amount depending on which input terminal the signal is switched to. In a preferred embodiment, the cascode transistors are driven differentially to conserve power supply headroom, and the bondwire and leadframe inductance of an integrated circuit are utilized as elements of the loading network. The loading network can be extended to include several stages that are implemented as a ladder such as an R/2R ladder with multiple cascode transistors to provide uniform multiple gain steps.

Abstract: Signal-controlled oscillator structures are provided that are substantially insensitive to temperature, supply voltages and fabrication processes. They include a plurality of time-delay stages that are serially connected in a closed feedback ring and each of the stages includes an amplifier, at least one capacitor and at least one signal-controlled impedance element that couples the capacitor to the amplifier. Accordingly, the frequency of the oscillator is a function of a control signal applied to the impedance elements of the stages. In an oscillator embodiment, each of the amplifiers is a differential pair of transistors, the capacitor comprises first and second capacitors and the signal-controlled impedance element comprises first and second coupling transistors that each couples a respective one of the capacitors to a different side of the differential output.

Abstract: A sigma-delta analog-to-digital converter includes an integrator having an input and an output and an integrator capacitor connected between the input and output. A switched-capacitor input circuit includes at least one input capacitor, an input sampling switching circuit and an input delivery switching circuit. The input sampling switching circuit includes at least one input sampling switch operable to connect the input capacitor to be charged by an input voltage at a sampling rate. The input delivery switching circuit includes at least one input delivery switch operable to connect the input capacitor to transfer charge to the integrator capacitor at a first transfer rate. A switched-capacitor feedback circuit is connected in a feedback path between the input and output of the integrator. The feedback circuit includes at least one feedback capacitor, a feedback sampling switching circuit and a feedback delivery switching circuit.

Abstract: A switched-transconductance circuit for use in a multiplexer circuit includes integrated T-switches to provide isolation between each of the differential voltage inputs of a transconductance stage and: (1) a respective differential current output of the transconductance stage, and (2) the opposite polarity voltage input of the transconductance stage. Each of a pair of first switches, which are enabled only when the transconductance circuit is disabled, is connected between a differential current output of the transconductance stage and a circuit ground. Each of a pair of second switches, e.g., cascode transistors, which are biased to be turned on only when the transconductance circuit is enabled, is coupled between the output of the transconductance stage and an output of the transconductance circuit. A third switch is connected between a common-emitter node of a differential pair of input transistors included in the transconductance stage and a circuit ground.

Abstract: An asymmetrical modem system wherein a modem at a first location transmits information to a modem at a second location on a downstream signal and the modem at the second location transmits information to the modem at the first location on an upstream signal. The system includes a first location transmitter section, having an N-point inverse frequency transform, for converting information into the downstream signal having up to (N/2)-1 carriers. A second location transmitter section having, an [(NL)/(2K)-point inverse frequency transform, converts information into the upstream analog signal having up to [(NL)/(2K)]-1 carriers, where K is the ratio of downstream signal bandwidth to upstream signal bandwidth and L is greater one. A receiver section at the first location, having an [NM/K]-point frequency transform, separates the upstream signal into up to [(NM)/(2K)]-1 upstream carriers, where M is greater than one.

Abstract: A differential current switch including a differential switch pair of transistors having first and second complementary control inputs which receive first and second complementary signals so as to be controlled by a control signal with equal delay from a clock signal. A first set of switching transistors is coupled to provide the first complementary signal which controls the first complementary control input of the differential switch pair. A second set of switching transistors is coupled to provide the second complementary signal which controls the second complementary control input of the differential switch pair. First delay transistor pairs are coupled to the complementary outputs of the cross coupled inverter and have the characteristic that the fall times of its outputs are greater than the rise time of its outputs. Second delay transistor pairs are coupled to the first delay transistor pairs and have the characteristic that the rise times of its outputs are greater than the fall times of its outputs.

Abstract: A discrete multi-tone, asymmetrical transceiver and method wherein a modem at a central office transmits information to a modem at a remote terminal on a down-stream signal and the modem at the remote terminal transmits information to the modem at the central office on an up-stream signal. The up-stream signal comprising data carried by a lower portion of a predetermined band of frequencies and the down-stream signal comprising data carried by an upper portion of the predetermined band of frequencies. The system includes an interpolator, at the remote terminal, for adding interpolated data into a stream of data distributed by the remote terminal modem among the lower portion of the predetermined band of frequencies for transmission in the up-stream signal. An ADC is provided at the modem of the central office, for converting the down-stream signal into digital samples at a sampling rate greater than the frequency of the highest frequency in the down-stream signal.

Abstract: A gain stage is disclosed for use in an amplifier which provides an output signal. The gain stage includes a first transistor including a base, an emitter and a collector. The base is coupled to an input signal applied to the gain stage, and the emitter is coupled to a first source of operating potential. The gain stage also includes a second transistor including a base, an emitter and a collector. The collector of the second transistor is coupled to the collector of the first transistor for providing the output signal. The emitter of the second transistor is coupled to a second source of operating potential. The gain stage also includes a level shifter coupled to both the input signal and the base of the second transistor. The level shifter provides level shifting and produces a gain signal responsive to the input signal.