Abstract: A transistor cell is provided that includes transistors arranged to turn on for different voltages applied to a control terminal of the transistor cell. The transistor cell can include a first transistor having a gate, a source, and a drain, and a second transistor having a gate, a source, and a drain, wherein the source of the second transistor is coupled to the source of the first transistor, and the drain of the second transistor is coupled to the drain of the first transistor. The transistor cell can further include a first resistor coupled between the gate of the first transistor and the gate of the second transistor. A frequency mixer is also provided that includes at least one transistor cell.

Abstract: A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and frequency down signals that adjust the frequency of the clock signal to be equal to the frequency of the data signal. A step control system is responsive to the rotational frequency detector and a step clock signal and is configured to define predetermined pulse widths for the frequency up and frequency down signals.

Abstract: An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

Abstract: A current driven DAC architecture uses a single resistance string arranged to have a cyclic configuration and a plurality of nodes, one of the nodes being connected to a known potential, e.g., ground potential, and at least two current sources connected to selected ones of said nodes through operable switches, and an output connected to a selected one of said nodes. In one modification, 22n?2 LSB (least significant bit) voltage levels are generated as outputs from 2n cyclic string resistors and two current sources. In another modification, spurious-free resolution of (2n?2) bits and (2n?1) bit resolution with lower SNDR are achieved by using 2n resistors and two current sources. In one described embodiment, 2n unit impedances in the cyclic string result in 2(n?1) bit resolution. Thus, the single cyclic string of resistances achieves the function of both MSB sub-string and LSB sub-string.

Abstract: A programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm includes a Galois field linear transformer system (GFLT) responsive to a first input data block to execute an E permutation to obtain an expanded data block and combine it with a key to obtain a second larger intermediate data block in one cycle; and further includes a parallel look-up table system for implementing the unique data encryption standard selection function(s) and for condensing the second larger intermediate data block to a third data block similar to the first input data block in a second cycle and submitting it to the Galois field linear transformer system to execute a second permutation in a third cycle resulting in a data encryption standard cipher function of the first input data block.

Abstract: The present application addresses the problem arising during the erasure of EEPROMs where the FN tunnelling erase cycle is not self-limiting. Existing methods address this problem by employing monitoring algorithms. However, these algorithms slow the erase procedure time. The present application provides an alternative method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The method comprises the initial step of raising the potential at the erase gate and lowering the potential at the control gate to cause FN tunnelling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a sufficient value to cause to start FN tunnelling through the oxide of the transistor. A new structure particularly suitable for this method is also disclosed.

Abstract: Buffer amplifiers are provided that demonstrate enhanced efficiency because they include current sources which are configured to be switched off during operational modes in which the amplifiers' output signals are not needed. Amplifier embodiments include charge-transfer transistors and filter capacitors that reduce spurious signals which may be generated by the switching operations.

Abstract: An amplifier output voltage swing extender circuit comprises a differential amplifier powered between first and second power supply rails, which receives first and second input signals at non-inverting and inverting inputs, respectively, and provides an output at a first output node. A level shifting circuit, preferably a voltage divider, is connected in series with the first output node and shifts the node voltage toward the second rail by a fixed amount; the shifted voltage is provided at a second output node. A feedback network couples the second output node voltage to the amplifier's inverting input, such that when a voltage VSET is applied to the non-inverting input, the maximum negative voltage excursion at the first and second output nodes is greater than the value of the VSET voltage with respect to the second supply rail.

Abstract: A method and apparatus for driving a current switch with a differential drive signal monitors both the temperature of the switch and the current through the switch. The method and apparatus dynamically control the amplitude of the drive signal as a function of the switch temperature and the current through the switch. The result is a significant reduction in base drive amplitude without compromise to offset and linearity performance of the driver. The resulting dynamic performance of the switch is substantially improved.

Abstract: A technique for allocating fingers in a path searcher of a multipath receiver involves determining a required number of fingers for each multipath region, determining a number of allocated fingers for each multipath region according to an area-based weighting scheme such that each multipath region that is allocated fewer than its required number of fingers is deemed to have a non-zero residual area, allocating any surplus fingers to multipath regions having non-zero residual areas until either no surplus fingers remain or each multipath region is allocated its required number of fingers, and placing any fingers allocated to each multipath region within the multipath region. Placing the fingers in un-resolvable path scenario involves detecting path location at the edges of multipath region; placing fingers at the edges and placing remaining fingers uniformly between the first and the last path such that the there is a minimum placement separation between the fingers.

Abstract: A sensor has a die (with a working portion), a cap coupled with the die to at least partially cover the working portion, and a conductive pathway extending through the cap to the working portion. The pathway provides an electrical interface to the working portion.

Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitized; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.

Abstract: Converter system embodiments are formed with signal-processing stages which include successive signal converters and a preceding signal sampler wherein all but a last one of the stages provides an output signal to a succeeding one of the stages and all of said signal converters generate a corresponding digital code. The system embodiments generally address a selected one of the stages and include controllers which are configured to process, at a process rate less than the system's sample rate, a digital error signal and the back-end digital code of back-end ones of signal converters that succeed the selected stage to thereby adjust at least one of the back-end digital code and a control voltage in the selected stage to enhance the accuracy of the system digital code. Once the processes of these embodiments have been applied to the selected stage, they may be successively applied to preceding stages. System embodiments are also directed to nonlinear amplifier gain by including approximations (e.g.

Abstract: An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal paths. The variable delay module is operable to delay a first clock signal on the delay path so that a bias input signal presented to the delay bias input, when a bias input signal is present, corresponds to the time delay between the first clock signal and a second clock signal on the target signal path.

Abstract: A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.

Abstract: An apparatus for biasing a transistor, comprising: a controllable bias generator; a test circuit; a digital Mth order differentiator responsive to an output of the test circuit; and a controller responsive to the digital Mth order differentiator for controlling the controllable bias generator; wherein the test circuit is configured to calculate an Lth order derivative of the transistor's performance.

Abstract: A reconfigurable input Galois field linear transformer system includes a Galois field linear transformer including a matrix of cells; a plurality of storage planes for storing control patterns representing a number of different functions; a storage plane selector circuit for selecting a storage plane representing a function for enabling the cells of the matrix which defines that function; and a reconfigurable input circuit for delivering input data to the enabled cells to apply that function to the input data.

Abstract: A rapid response measurement is accomplished by providing to a programmable gain amplifier an input to be measured, providing to an analog to digital converter having a predetermined output rate, the output from the programmable gain amplifier, determining when the output is greater than full scale input range of the analog to digital converter in an interval shorter than the period of the predetermined output rate of the analog to digital converter and adjusting the gain of the programmable gain amplifier to reduce the output below the full scale of the analog to digital converter at a rate faster than the predetermined output rate of the ADC.

Abstract: Reference network embodiments are disclosed that provide reference signals to, for example, switched-capacitor multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters (ADCs). These embodiments are configured to maintain accuracy of the levels of the reference signals in the presence of high speed charge-injection and charge-extraction currents which are presented by the MDACs.

Abstract: A packet detection technique is disclosed in which an average correlation signal is generated representative of the match between a repetitive sequence of symbols; an average power signal is generated representative of the average power in the sequence of symbols; a scaled magnitude of the average correlation signal scaled by a first predetermined scale factor is produced; and one of the average power signal and scaled magnitude of the average correlation signal are multiplied by the second scale factor and compared to determine whether there is a match between a repetitive sequence of symbols.