Abstract: A DC-to-DC converter includes an error integrator that further includes a first amplifier and a second amplifier that each includes a first input for receiving a reference voltage and a second input for receiving a feedback voltage, a capacitor to an output of the second amplifier, and a resistor including a first end being coupled to an output of the first amplifier and a second end being coupled to the capacitor.

Abstract: A method according to an embodiment of a system for efficient resource management of a signal flow programmed digital signal processor code is provided and includes determining a connection sequence of a plurality of algorithm elements in a schematic of a signal flow for an electronic circuit, the connection sequence indicating connections between the algorithm elements and a sequence of processing the algorithm elements according to the connections, determining a buffer sequence indicating an order of using the plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence, and reusing at least some of the plurality of memory buffers according to the buffer sequence.

Abstract: A MEMS device with movable MEMS structure and electrodes is produced by fabricating electrodes and shielding the electrodes with diamond buttons during subsequent fabrication steps, such as the etching of sacrificial oxide using vapor HF. In some embodiments, the diamond buttons are removed after the movable MEMS structure is released.

Abstract: A MEMS sensor includes a substrate and a MEMS structure coupled to the substrate. The MEMS structure has a mass movable with respect to the substrate. The MEMS sensor also includes a reference structure electrically coupled to the mass of the MEMS sensor. The reference structure is used to provide a reference to offset any environmental changes that may affect the MEMS sensor in order to increase the accuracy of its measurement.

Abstract: One embodiment relates to an apparatus configured to cancel charge injected on a node of a differential pair of nodes. A dummy circuit element can inject charge on an inverted node to cancel charge injected on a non-inverted node by a switch when the switch is switched off. In addition, another dummy circuit element can inject charge on the non-inverted node to cancel charge injected on the inverted node by another switch when the other switch is switched off. These dummy circuits elements can be cross-coupled.

Abstract: An apparatus for limiting the bandwidth of an amplifier provides for the design of an input impedance, a feedback impedance, and a load impedance such that the load impedance is proportional to the sum of the input impedance and feedback impedance. A sampling circuit has a load impedance including a resistor and capacitor in series to reduce the effective amplifier transconductance, which decreases bandwidth without increasing noise density or making this circuit more difficult to drive than a conventional circuit.

Abstract: An electrical circuit includes a comparator that receives a first signal at a first input pin, where the first signal is indicative of a current drawn from a power supply unit (PSU) that delivers power to an electronic component. The comparator substantially simultaneously receives a second signal at a second input pin, where the second signal is indicative of a voltage provided by the PSU to the electronic component and is set to a predetermined threshold. An output of the comparator changes if a difference exists between the first signal and the second signal. The electrical circuit includes a variable gain amplifier that provides the first signal to the comparator, where a gain of the variable gain amplifier is set according to the predetermined threshold.

Abstract: Embodiments of the present invention may provide a device to adaptively generate a haptic effect. The device may include a controller to generate a haptic command associated with a haptic profile and a haptic driver to generate a drive signal based on the haptic command, wherein the drive signal causes an actuator to produce vibrations corresponding to a haptic effect. Further, the device may include a sensor, coupled mechanically to the actuator, to measure at least one property of the vibrations. The controller may adjust the haptic command according to the measured at least one property. Therefore, the device may continuously tune haptic effect generation according to vibration measurements.

Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.

Abstract: In one example implementation, the present disclosure provides a modular approach to reducing flicker noise in metal-oxide semiconductor field-effect transistors (MOSFETs) in a device. First, a circuit designer may select one or more surface channel MOSFETs in a device. Then, the one or more surface channel MOSFETs are converted to one or more buried channel MOSFETs to reduce flicker noise. One or more masks may be applied to the channel(s) of the one or more surface channel MOSFETs. The technique maybe used at the input(s) of operational amplifiers, and more particularly, rail-to-rail operational amplifiers, as well as other analog and digital circuits such a mixers, ring oscillators, current mirrors, etc.

Abstract: In one embodiment, a measuring device may comprise two oscillators. The first oscillator may generate a local reference signal in a frequency detector to detect a fundamental frequency of the AC. The second oscillator may generate two substantially mutually orthogonal sinusoid signals having the selected frequency. The measuring device further may comprise a first group of multipliers that mixes the two sinusoid signals with a current and a voltage data signal of the AC respectively, a group of low-pass filters for removing high frequency components from the multiplication products, a second group of multipliers for mixing the filtered multiplication produces respectively, and a plurality of adders each to sum together a pair of multiplication products of the second group of multipliers.

Abstract: A system and method provide for calibrating the frequency response of an electronic filter. The system and method include a radio transmitter with both in-phase and quadrature baseband paths. Each baseband path includes a numerically controlled oscillator (“NCO”), a digital signal path, a digital-to-analog converter (“DAC”), and an analog filter. A low frequency tone is applied from the NCO from one of the baseband path, while a high frequency tone is applied from the NCO in the other baseband path. An analog peak detector at output determines which analog filter has the largest amplitude at the output. The peak detector offset between the two analog filters is offset by stimulating the in-phase and quadrature baseband paths with the respective NCOs to find an amplitude difference between the output signals from the NCOs that makes the output of the analog filters the same.

Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.

Abstract: According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase.

Abstract: A method for identifying objects in a digital image includes tracing chain codes associated with the contour of the object; a series of states is maintained, and the next chain codes in the contour are accepted only if they comply with allowed chain codes for each state. Certain chain codes trigger a transition into a next state. If a disallowed chain code is encountered, the process halts.

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.

Abstract: A system may include a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal. A delay circuit may be included to receive the clock signal and provide a delayed clock signal that lags the clock signal by an amount representing a delay across the isolation barrier. The delayed clock signal may be delayed by a round trip propagation delay over the isolation barrier. The delayed clock signal may be used as a reference to read data sent over the isolation barrier.

Abstract: A low dropout voltage regulator (LDO) includes first and second amplifiers and a current mirror. The first amplifier includes a first input receiving a reference voltage and a second input receiving a voltage proportional to an output of the LDO. The current mirror includes an input current at a first end of the current mirror to an output current at a second end of the current mirror, the input current controlled by an output of the first amplifier and the output current being supplied to the output of the LDO. The second amplifier includes a first input coupled to the first end of the current mirror and a second input coupled to the second end of the current mirror.

Abstract: An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.

Abstract: A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately.