Abstract: A system implementing an MBIST device is disclosed. The system includes an ECC-protected memory and the MBIST device for self-test of the memory. The MBIST device includes a first access port communicatively connected to the memory via a first path, the first path excluding the ECC logic associated with the embedded memory, and a second access port communicatively connected to the memory via a second path, the second path including the ECC logic associated with the memory. The device is configured to test the memory, in a first mode of operation, via the first path and, in a second mode of operation, via the second path. One advantage of such system includes re-using, with little additional die area, of MBIST logic already required for manufacturing test of the product (first mode of operation) for system or application level tests that may be carried out by customers (second mode of operation).

Abstract: Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.

Abstract: In an example, a system and method are disclosed for providing a single control law that is operable to regulate both small-signal, steady-state operation, and large-signal transients of a switching regulator. The control law is based on detecting a zero-crossing of capacitor current, and projecting in advance a turning point for either ramping up or ramping down capacitor voltage at a target voltage. Certain embodiments may realize the control function in high-speed analog components, although certain other embodiments may implement the same or a similar control law in a digital controller.

Abstract: In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.

Abstract: A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.

Abstract: Determining if a hermetically sealed MEMs device loses hermeticity during operation. In one embodiment, the MEMs device is an accelerometer. A test signal having an associated frequency above an operational frequency range for the accelerometer is provided to the accelerometer at an input during operation of the accelerometer for sensing an acceleration. The output signal of the accelerometer is filtered at least above the operational frequency range of the accelerometer producing a test output signal. The test output signal is then compared to a predetermined threshold to determine if the amplitude of the test output signal differs from the threshold. If the amplitude of the test output signal differs from the predetermined threshold, an error signal is produced indicating that hermeticity of the accelerometer has been lost.

Abstract: Electrostatic discharge (ESD) protection devices can protect electronic circuits. In the context of radio frequency (RF) circuits and the like, the insertion loss of conventional ESD protection devices can be undesirable. The amounts of parasitic capacitances at nodes of devices of an ESD protection device are not necessarily symmetrical, with respect to the substrate. Disclosed are techniques which decrease the parasitic capacitances at signal nodes, which improve the insertion loss characteristics of ESD protection devices.

Abstract: An optical detector may include an epitaxial layer having a continuous surface provided on a surface of a substrate. Two or more electrodes may be arranged at different positions in the epitaxial layer so that the electron-hole pairs generated in the epitaxial layer from incident light passing through the aperture and reaching the epitaxial layer have a varying probability of being collected by each of the electrodes as the angle of the incident light changes. The electrodes may be arranged at different depths in the epitaxial layer. The epitaxial layer may be continuous and have a continuous aperture-facing surface between each of the electrodes associated with a particular aperture to ensure that more light passing through the aperture is absorbable in the epitaxial layer and subsequently detectable by the electrodes. This may result in improved light detection capabilities.

Abstract: In certain example embodiments, a system is provided that includes a circuit. The system also includes a reverse current control module that provides an isolated power supply in order to protect one or more devices in a power chain during one or more testing activities having one or more requirements.

Abstract: An integrated circuit can include a group of bond pads alternating between bond pads configured to provide a return path and bond pads configured to provide a signal bond pad. For example, five bond pads can be arranged in a return-signal-return-signal-return arrangement. The integrated circuit can further be configured to receive or transmit high frequency signals.

Abstract: In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality of openings. The metal pads are vertically aligned and the placement of the openings in each metal pad is such that the openings are laterally offset and substantially do not directly overlie or underlie one another. As seen in a top-down view, the through-silicon via etch may “see” a metal etch stop that extends continuously across the width of the via, although different portions of the etch stop may be distributed on different vertical levels due to the presence of openings in the metal pads. The openings in the metal pads facilitate integrated circuit fabrication their respective levels and the aggregate structure formed by the metal pads provides an effective etch stop for the through-silicon via etch.

Abstract: In an example, a differential amplifier is disclosed that is configured to realize low noise with decreased overall system current. The differential amplifier may include a first amplifier stage and a second amplifier stage arranged in series, wherein a pull-up current iH flowing as a single bias current iB=iH flows into the first stage. A single pull-down current iT sources to ground from the second stage, wherein iH=iT=iB substantially. In certain embodiments, the transconductance of the second stage may be increased by providing two transconductors coupled at their base nodes.

Abstract: It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate Fs and to output data at an output sample rate Fo, where Fo=Fs/N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels.

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract: A charge pump cell, comprising: an input node; an output node; Q channels, where Q is an integer greater than one, and where at least two of the channels comprise: a capacitor; a unidirectional current flow device; an output diode; and a channel drive signal node; and wherein a first current flow node of the unidirectional current flow device is connected to a first node of the capacitor at a channel node, a second node of the capacitor is connected to the channel drive signal node, a second current flow node of the unidirectional current flow device is connected to the input node, and the output diode is connected between the channel node and the output node.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: A method for downsampling digital samples xn, . . . of a signal by a decimation factor d comprising an integer part i using averaging is disclosed. The method includes identifying a partial sum based on the decimation factor and a number N of samples to use for the averaging as a sum Sn+i,n+N?1 of (N?i) samples xn+i, . . . xn+N?1, computing the partial sum, computing a first sum Sn,n+N?1 of a first set of N digital samples xn, . . . xn+N?1 as a sum of a set of i digital samples xn, . . . xn+i?1 and the computed partial sum, computing a second sum Sn+i,n+i+N?1 of a second set of N digital samples xn+i, . . . xn+i+N?1 as a sum of a set of i digital samples xn+N, . . . xn+i+N?1 and the computed partial sum, and downsampling the digital samples based at least in part on the first sum and the second sum.

Abstract: Data converters convert signals in analog form to digital form or from digital form to analog form. Due to mismatches between devices that are intended to be identical (unary elements), some data converters outputs may have undesirable characteristics, such as non-linearities. Shuffling the inputs to the unary elements based on a pseudo-random sequence is a technique that can average out the mismatches over time. However, shuffling generally requires a complex switch matrix, and can potentially impact the speed of the converter. To address mismatches, a high speed technique for rotating comparator thresholds is implemented to effectively rotate an array of unary digital-to-analog converter elements. The technique is particularly advantageous for addressing mismatches in unary digital-to-analog converters used for reconstructing a quantized analog signal within delta-sigma analog-to-digital converter.

Abstract: In this disclosure, new structures for high-performance voltage buffers (source followers and emitter followers) are described. The structures achieve high performance (linearity) and reduce power consumption. In addition, they are reconfigurable to optimize the performance and power consumption depending on the input frequency range.

Abstract: A circuit operating with a switching clock signal and a sampling clock signal can have one or more of its switching and sampling clock signals periodically phase-reversed. The period of phase reversal can be greater than twice the period of the original switching and/or sampling clock signal, and in certain configurations the switching and sampling clock signals can be synchronized. With a selection of phase reversal period (or frequency), aliasing frequency components of the mixed signal from the switching and sampling clock signals can be removed.