Abstract: In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port.

Abstract: A switching power converter circuit comprises an input port, a first circuit supply rail having a first positive voltage greater than circuit ground, a second circuit supply rail having a second positive voltage greater than circuit ground, and an inductor electrically coupled to the input port, wherein inductor current flows in a first direction through the inductor to generate the first circuit supply rail and flows in an opposite direction through the inductor to generate the second circuit supply rail.

Abstract: A current amplifier is disclosed. The circuit has differential input and output and can be implemented in CMOS or bipolar integrated-circuit technologies. The input current is injected into a pair of primary branches, and is re-used at the output of the circuit without changing its natural flow, thus contributing to the overall current gain. A pair of secondary branches is connected to the primary branches in such a way as to provide currents proportional to the input currents according to a scaling factor dictated by the geometry of the transistors. The outputs of the secondary branches are cross-coupled relative to the outputs of the primary branches, in this way ensuring maximum current gain by the summing of the primary and secondary signal currents at the circuit output, without consuming additional DC power.

Abstract: A laterally coupled isolator includes a pair of isolator traces provided in a common dielectric layer and separated by a distance that defines the isolation strength of the system. Circuit designers can vary the lateral distance to tailor isolation rating to suit individual design needs. A second embodiment includes a semiconductor substrate, provided below the isolator traces that includes a communication circuit electrically coupled to one of the isolator devices.

Abstract: Aspects of this disclosure relate to protecting a circuit, such as an amplifier, from transient overdrive events and/or average overdrive events. In one embodiment, an indication of average power, such as root mean squared (RMS) power of a radio frequency (RF) signal, can be compared to a first threshold and an indication of a peak RF power can be compared to a second threshold. When the indication of average power exceeds the first threshold, an average overdrive event can be detected. When the indication of peak power exceeds the second threshold, a peak overdrive event can be detected. If either a transient overdrive event or an average overdrive event is detected, a circuit, such as an amplifier, can be protected.

Abstract: A magnetic direction sensor, comprising a first array of magneto-resistive elements, said array having a first array primary direction and wherein some but not all of the magneto-resistive elements are wholly or partially provided at a first angle to the primary direction, and the remaining elements are also inclined with respect to the primary direction.

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).

Abstract: A low-cost system comprising a pattern arranged to encode information and a decoder for decoding the information encoded in the pattern is described. In particular, the mechanism employs a capacitive sensing technique. Electrodes are arranged (or stimulated, during operation) to each generate an electric field, and sense disturbances on the electric field caused by the pattern when the pattern is positioned over the electrodes. The spatial arrangement of the pattern allows information to be encoded on a strip or surface and decoded by capacitive sensors arranged to detect disturbances caused by possible patterns. The resulting solution is cheaper and less complex than optical solutions, e.g., barcodes and optical barcode readers. The mechanism may be used in a glucose meter for encoding and decoding an identifier for distinguishing batches of glucose meter test strips.

Abstract: Apparatus and methods for radio frequency (RF) switches are provided herein. In certain implementations, an RF switching circuit includes an adaptive switch bias circuit that controls gate and/or channel voltages of one or more field effect transistor (FET) switches. Additionally, the adaptive switch bias circuit is powered by a power high supply voltage and a power low supply voltage, and can be used to selectively turn on or off the FET switches based on a state of one or more switch enable signals. The adaptive switch bias circuit adaptively biases that gate and/or channel voltages of the FET switches based on a voltage difference between the power high and power low supply voltages to provide switch biasing suitable for use with two or more different power supply voltage levels.

Abstract: A hybrid, translinear amplifier has at least one gain stage including first and second gain transistors, at least a first load transistor electrically coupled to the first gain transistor and at least a second load transistor electrically coupled to the second gain transistor, and load resistors electrically coupled to the load transistors. A hybrid, translinear amplifier with selectable gain has a first hybrid, translinear amplifier cell having at least first and second load transistors, each load transistor having a load resistor, at least one additional hybrid, translinear amplifier cell having at least third, fourth, fifth and sixth load transistors, each load transistor having a load resistor, at least two switches electrically coupled to the amplifier cells to allow selection of one of the amplifier cells, and a differential output signal having a gain corresponding to a selected amplifier cell.

Abstract: A motor driver may include a controller, a space vector modulator, a converter and a detector. The space vector modulator may generate driving signals under control of the controller according to a space vector pulse width modulation (“SVPWM”) scheme. The converter may derive AC signals from the driving signals received from the space vector modulator and may output the AC signals to the USM motor. The detector may generate feedback signals representing current and voltage supplied to the USM motor. The controller may revise estimates of space vectors, based on measurements from the detector, to control the space vector modulator to adjust frequencies, amplitudes, or phase angles of the plurality of AC signals.

Abstract: The present application relates in one aspect to a method of controlling diaphragm excursion of an electrodynamic loudspeaker. The method comprises dividing the audio input signal into at least a low-frequency band signal and a high-frequency band signal by a band-splitting network and applying the low-frequency band signal to a diaphragm excursion estimator. The instantaneous diaphragm excursion is determined based on the low-frequency band signal. The determined instantaneous diaphragm excursion is compared with an excursion limit criterion. The low-frequency band signal is limited based on a result of the comparison between the instantaneous diaphragm excursion and the excursion limit criterion to produce a limited low-frequency band signal which is combined with the high-frequency band signal to produce an excursion limited audio signal.

Abstract: A drive system for multiple LED strings powered by a common line voltage. Current control circuits are connected in series with respective LED strings; each current control circuit includes a drive transistor (typically a FET) which causes a desired LED string current to be conducted. In one embodiment, the current conducted by a selected one of the LED strings is controlled by the line voltage regulation loop, while the currents conducted by the remaining LED strings are controlled by respective local current loops, thus avoiding conflicts between the local current and line voltage regulation loops. The LED string to be current regulated by the line voltage regulation loop can be determined by a variety of criteria, such as the current control circuit having the maximum FET gate voltage, the minimum FET source voltage, the minimum FET drain voltage, the maximum FET gate-source voltage, or the minimum FET drain-source voltage.

Abstract: A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.

Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

Abstract: Apparatus and methods for switch-coupled oscillators are disclosed. In certain implementations, an oscillator system includes a primary oscillator, one or more auxiliary oscillators, one or more switching circuits, and an oscillator control circuit. The oscillator control circuit can be used to control the one or more switching circuits to selectively couple the primary oscillator to all or a portion of the one or more auxiliary oscillators. The oscillator control circuit can also disable any auxiliary oscillators that are decoupled from the primary oscillator to reduce power consumption. By selecting a number of auxiliary oscillators to couple to the primary oscillator, the oscillator system can have a configurable phase noise versus power consumption profile.