Abstract: An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal.

Abstract: Aspects of this disclosure relate to reference switchover. In one embodiment, an apparatus includes a phase error detector, a phase alignment detector, and a selection circuit. The phase error detector is configured to generate an indication of a relative phase difference between a first reference clock signal and a second reference clock signal. The phase alignment detector is configured to receive the indication of the relative phase difference and determine when the relative phase difference satisfies a preset threshold. The selection circuit is configured to transition from providing the first reference clock signal as a clock system reference signal to providing the second reference clock signal as the clock system reference signal responsive to the phase alignment detector detecting that the relative phase difference satisfies the preset threshold.

Abstract: Embodiments of the present disclosure provide improved switching techniques for controlling three-level DAC cells employing a return-to-hold scheme. Disclosed techniques include switching a DAC cell off for at least the duration of a time period between two hold periods while a digital value of zero is being converted. Because the DAC cell is switched off between two hold periods, the current source drain voltage is not disturbed during the critical transient times when D flip-flop outputs change, which happens during the hold periods, in response to change of digital values to be converted. In this manner, power consumption may be reduced while preserving the high performance properties of a three-level return-to-hold DAC.

Abstract: A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.

Abstract: A device has at least two current mode logarithmic amplifiers having currents as their inputs, and multiplexing logic electrically connected to outputs of the current mode logarithmic amplifiers to select one of the current mode amplifiers to produce an output signal.

Abstract: Circuits for generating voltage references are common in electronics. For example, these circuits are used in analog-to-digital converters, which convert an analog signal into its digital representation by comparing analog input signals against one or more voltage references provided by those circuits. In many applications, the speed and accuracy of such voltage references are very important. The speed of the voltage references is related to the physical properties of the devices in the circuit. The accuracy of the voltage reference is directly related to the circuit's ability to trim the full-scale voltage output. The present disclosure describes a fast and efficient reference buffer with a wide trim range which is particular suitable for submicron processes and high speed applications. The reference buffer comprises a plurality of diode-connected transistors, which can be selected to turn on or off using a controller to provide a wide trim range.

Abstract: For small cells, transceivers demand high performance while maintaining system efficiency. The present disclosure describes a highly integrated cellular transceiver that offers such features by providing one or more digital functions on-chip, onto the same die in the cellular transceiver. Effectively, the scope and boundary of the cellular transceiver is expanded to move beyond the data converters of the transceiver to include a variety of digital functions, thus integrating more of the signal chain in the cellular transceiver. Integration can greatly reduce complexity for the baseband processing, lower the cost of the overall transceiver system, reduce power consumption, and at the same time, benefit from improvements on the digital functions through integration.

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract: A device to detect an electrical signal is provided. The device includes sensing, output, and pull-down nodes. The device includes a pull-down circuit having a native metal-oxide-semiconductor field-effect transistor (MOSFET) to pull down the output node to approximately a voltage of the pull-down node. The device includes a switch circuit having a junction field-effect transistor (JFET). The JFET turns on the pull-down circuit in response to a voltage of the sensing node being less than a first threshold. The JFET also turns off the pull-down circuit in response to the voltage of the sensing node being greater than the first threshold.

Abstract: The invention may provide a temperature sensor device that includes an analog temperature sensor to generate a first base-emitter voltage and a second base-emitter voltage, and an analog-to-digital converter (ADC) to sample at the voltages and generate corresponding digital values. The temperature sensor device may also include a logic unit to calculate a digital temperature code from the digital values using a digital virtual reference.

Abstract: Trigger routing in computational hardware such as a digital-signal processor involves routing a trigger signal from a first, master module to a second, slave module, thereby initiating an event at the slave module without involving a core processing unit.

Abstract: An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.

Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.

Abstract: Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.

Abstract: Active Noise Cancellation (ANC) systems and methods that reduce latency to improve performance. In certain embodiments the systems sample a noise signal using a sample period to create a stream of digital signal data that is representative of the noise signal. A data transport layer carries the digital signal data to a signal processor. The transport layer temporally organizes the digital signal data to place the digital signal data within an initial phase of a sample period. The remaining phase of the sample period is set to a duration that allows the signal processor to process the digital signal data carried in the initial phase and to output the processed data during the same sample period. In this way, the processing of data occurs within one sample period and the latency is reduced and predictable.

Abstract: The present invention relates to power conversion apparatus (40) configured to receive a high voltage alternating current (AC) signal at an input (42, 44) and to provide in dependence thereon a low voltage direct current (DC) signal from an output stage (58, 60). The power conversion apparatus (40) comprises a main path comprising a high voltage capacitor (46) in series with the input. The power conversion apparatus (40) also comprises a first path operative to carry current carried by the main path in at least one of a positive going part and a negative going part of the high voltage alternating current signal and a second path operative to carry current carried by the main path in a positive going part and a negative going part of the high voltage alternating current signal. The power conversion apparatus further comprises first and second switches (52, 54) which are operative to determine when a respective one of the first and second paths carries current.

Abstract: Aspects of this disclosure relate to compensating for a relatively large offset in a signal generated by a sensor, such as a pressure sensor and/or a resistive bridge based sensor. Such offset compensation can include applying an offset correction signal generated by a configurable voltage reference, such as a voltage mode digital-to-analog converter (DAC), to an input of an amplifier included in an instrumentation amplifier to compensate for the offset of the signal generated by the sensor.

Abstract: Mechanical resonating structures, as well as related devices and methods of manufacture. The mechanical resonating structures can be microphones, each including a diaphragm and a piezoelectric stack. The diaphragm can have one or more openings formed therethrough to enable the determination of an acoustic pressure being applied to the diaphragm through signals emitted by the piezoelectric stack.

Abstract: A computer program product and method for using a computer program product for graphically developing a computer program for execution at least in part on a separate host processor device, such as, a digital signal processor. The computer program product includes code for providing a graphical programming environment. The computer code which is used for developing the computer program includes a cell module for graphically representing a graphical control. The cell module does not contain any host processor specific code. The cell module may include code for rendering on the display of the computer that is operating as the programming environment one or more graphical controls. The cell module may also contain host processor independent code that accepts input from a user (parameter value) and converts the parameter value or applies an equation to the parameter value.

Abstract: A system that incorporates the subject disclosure may include, for example, a method for producing an electrical signal from an apparatus comprising an induction coil coupled to a mechanical resonator, wherein the electrical signal has an operating frequency proportional to a mechanical resonating frequency of the mechanical resonator and proportional to a change in a magnetic flux resulting from a change in orientation in the apparatus, detecting with a detection circuit a change in the electrical signal resulting from a change in the magnetic flux caused by the change in orientation in the apparatus, and determining a direction of the apparatus according to the change in the electrical signal. Other embodiments are disclosed.