Abstract: In an example, there is disclosed herein a digital-to-analog converter (DAC) including a correction circuit for a clock, including a differential clock. Error correction may take place within the DAC core, by means of replica cells that are substantially similar to conversion cells. Rather than contributing their output to the converted signal, the replica cells may be configured to provide a feedback signal to a clock receiver with information for correcting the clock signal. The feedback signal may be operable to correct errors, for example, in duty cycle and crosspoint, as measured at the DAC core.

Abstract: A system and method for classifying touches input into a four-wire resistive touch screen is presented. A voltage may be applied to electrodes in a layer making it the active layer. A first set of four voltages may be measured by a voltage sensing circuit from electrodes in the active layer of a touch screen and a passive layer of a touch screen. The voltage may be switched from electrodes of the first layer to the electrodes of the second layer. A voltage sensing circuit may measure a second set of four voltages nearly simultaneously from electrodes in the active layer and the passive layer of a touch screen. Each set of measured voltages from the passive layer and or the active may be processed. A rule set may be applied to the processing results. An indication of the type of touch that was applied to the touch screen may be provided and optionally including quantitative results.

Abstract: A voltage measurement apparatus is provided that includes: a potential attenuator configured to be electrically connected between first and second conductors, which are electrically coupled to a source, wherein the potential attenuator includes a first impedance and a reference impedance arrangement in series with each other, wherein the reference impedance arrangement has an electrical characteristic that can be changed in a known fashion; and further including a processing arrangement configured to acquire at least one signal from the reference impedance arrangement, the at least one signal reflecting change of the electrical characteristic in the known fashion; and to determine a voltage between the first and second conductors in dependence on the fashion in which the electrical characteristic is changed being known and the at least one signal.

Abstract: A circuit to detect states of a signal is provided. The circuit comprises an input node to receive an input signal. A state detection circuit detects a state of the input signal and generates a detection signal. The state corresponds to at least one of three states. Furthermore, the detection signal generated by the state detection circuit has a level based on the detected state of the input signal. A logic discriminator circuit generates first and second state signals based at least partly on the level of the detection signal. A clock detection circuit generates a clock signal based at least partly on a sequence of logic transitions of the first and second state signals.

Abstract: A method of etching a plurality of cavities in a wafer provides a wafer having a patterned hard mask layer. The patterned hard mask has open areas defining locations for first cavities and second cavities. A mask is applied to cover the patterned hard mask layer. The mask is etched to remove wafer material from areas defined by the second cavities. The mask is removed and etching then removes wafer material except as prevented by the hard mask layer. This leaves the first cavities with a first depth and further deepens the second cavities to a depth greater than the first depth. By suitably configuring the second cavities, a capped die can be formed by securing the wafer to a second wafer and removing at least a portion of the unsecured side of the first wafer to expose the second cavities, thereby forming a plurality of caps on the second wafer.

Abstract: A transducer amplification circuit may include a preamplifier circuit with a signal input receiving a transducer signal to provide an amplified transducer signal comprising audible frequency components and ultrasonic frequency components. The transducer amplification circuit may include a first sigma-delta modulator configured to sample and quantize the amplified transducer signal to generate a first digital transducer signal comprising a first quantization noise signal. The first sigma-delta modulator may include a first noise transfer function having a high pass response in at least a portion of an audible frequency range to push the quantization noise signal to ultrasonic frequencies. A second sigma-delta modulator is configured to sample and quantize the amplified transducer signal to generate a second digital transducer signal comprising a second quantization noise signal.

Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract: A connection apparatus for controlling the supply of electrical power to a load, the connection apparatus comprising first and second electrically controllable devices connected in parallel to each other and in series with the load; wherein the first and second electrically controllable devices are dissimilar, and where a safe operating area product of voltage, current and safe operating area time for the first device is greater than the product of voltage, current and the same safe operating area time for the second device, and an on state resistance for the second device is less than an on state resistance for the first device, and where a controller is provided to use the first device for a first period of time to power up the load, and thereafter the second device is used to maintain power to the load.

Abstract: A stage of a pipelined analog-to-digital converter can include first and second pluralities of digital-to-analog converters (DACs), the first plurality sufficient in number to produce a residue from the stage, the second plurality having their outputs added into an analog output of the stage. A mapping circuit can exchange inputs between selected ones of the first and second pluralities of DACs, and a calibration circuit can provide first and second calibration signals to the selected one of the first plurality and another of the second plurality of DACs. The calibration signals can correlate to each other, but be uncorrelated to an analog input and digital output of the stage, and have unequal and partially offsetting effects on the stage's residue. A correction circuit can correct the digital output of the stage for circuit path errors based on a correlation between the calibration signals and an output of a succeeding stage.

Abstract: Certain example embodiments of the present disclosure can provide a parallelized atomic increment. A vgather instruction returns to a plurality of processing elements the value of a memory location. A vgather_hit instruction returns to a function of the number of “hits” to the memory location. In one embodiment, the function is unity. In another embodiment, the function is the number of hits having an ordinal designation less than or equal to the processing element receiving the return value.

Abstract: Apparatus and methods calibrate one or more gain ranges for errors. A system can identify offset error and amplification error that occurs when the system transitions from amplifying an input signal by a first gain factor to amplifying the input signal by a second gain factor. To identify the amplification error, the system can compare the slope of the data signal in a source or reference gain range with the slope of the data signal in the destination gain range. To identify the offset error, the system can compare the amplitude of the data signal in a destination gain range with an expected value in the destination gain range.

Abstract: A security-aware master is provided, such that a master can determine its security state before attempting access to secure resources or before requesting secure access level. An exemplary system include a system interconnect; one or more masters coupled with the system interconnect; and a master security check register coupled with the system interconnect. The master security check register is configured to receive a request from a master via the system interconnect to access the master security check register, wherein the request includes a master operating state signal that indicates a security state of the master requesting access, and return a data value to the master based on the master operating state signal, wherein the data value indicates a current security state of the master requesting access.

Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.

Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.

Abstract: An example embodiment of an active cascode circuit has a control circuit for control of the gate to source voltage (VGS) of at least one transistor in the active cascode circuit. The embodiment may be configured so that control of the VGS also controls the voltage Vin on the input. Vin may be adjusted without altering the device geometry or changing the drain current. This allows for better control and optimization of available headroom for the input voltage in low voltage designs and also results in higher active cascode circuit bandwidth and/or higher output impedance (Rout) for a given power level.

Abstract: Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy, and the package lid and the package substrate define a package interior. The package lid includes an interior coating suited to good adhesion with the epoxy, and an exterior coating suited to RF shielding, where the materials of the interior and exterior coatings are different. In one example, the interior lid coating is nickel whereas the exterior lid coating is tin.

Abstract: A plethysmography (“PPG”) measurement system may include at least one source of PPG radiation and at least one auxiliary sensor for detection of PPG radiation. The radiation source emits a portion of the PPG radiation toward a subject and another portion along an optical path for direct communication between the PPG radiation source and the auxiliary sensor. The auxiliary sensor may develop a profile against which measurements from primary PPG sensors, which receive light returning from the subject, may be compared. From this comparison, new PPG signals may be generated that exhibit lower noise than the PPG signals output by PPG sensors. These noise mitigation techniques may be used advantageously by a PPG system to generate more accurate measurements and also to reduce power consumption by the radiation sources.

Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, an amplifier includes first and second input terminals, an amplification circuit, a feedback circuit, and a current mirror. The amplification circuit includes a non-inverting voltage input electrically connected to the first input terminal and to a bias voltage, an inverting voltage input electrically connected to the second input terminal, a voltage output, and a current output. The amplifier includes a first feedback path from the voltage output to the inverting voltage input through the feedback circuit and a second feedback path from the current output to the inverting voltage input through the current mirror, which can mirror a current from the current output to generate a mirrored current. A current source such as a transducer can provide an input current between the first and second input terminals, and the mirrored current can substantially match the input current.

Abstract: A multi-level amplifier including a converter circuit being supplied with a supply voltage and operable to generate at least two output voltages, a voltage comparator circuit adapted to compare each of the output voltages with the supply voltage to generate a driving signal, and an amplifier circuit being supplied with an analog input signal, the amplifier circuit including an analog-to-digital converter coupled to a power stage driver and power stage, wherein the power stage driver receives the driving signal from the voltage comparator.