Abstract: A device or system that incorporates teachings of the present disclosure may include, for example, a resonant structure having a plate, a mass and a set of electrodes. The plate can have an extensional mode at a frequency when excited. The set of electrodes can be used to measure an acceleration of the mass when the acceleration of the mass changes the frequency of the plate. Other embodiments are disclosed.

Abstract: A circuit may include a detector, an approximator, a look-up table, a scaler, and an integrator. The detector may generate a first difference signal and a second different signal based on an input and an output. The approximator may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table may select one of a plurality of scaling factors based upon the index. The scaler may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator may generate the output based on the adjusted first difference signal and the adjusted second difference signal.

Abstract: A symmetric object in an image is identified by (a) converting an edge map of the acquired image into a binary image map including binary pixel values; (b) dividing the binary image map within a scanning window into multiple bins; (c) summing binary pixel values in each bin; and (d) identifying the symmetric object based at least in part on the summed binary pixel values in the bins.

Abstract: A method and system for encoding an analog signal on a stochastic signal, the encoded signal then converted to a digital signal by an analog to digital converter, the analog to digital converter thereafter decoding from the encoded signal a digital signal, which corresponds to the analog signal. The stochastic signal may be a noise signal shaped to a Gaussian normal curve. An encoding process is performed by a multiplication circuit, which multiplies the stochastic signal by the analog signal, producing a product signal for an analog to digital conversion. During analog to digital conversion, the product signal is decoded. The decoding is performed using an arithmetic operation, which may be a Root Sum Square function or a Root Means Square function. The decoded signal is then mapped to account for offset error, gain error, and endpoint adjustment. The result is a decoded digital signal corresponding to the analog signal.

Abstract: A hearing instrument has a plurality of electronic components within a body, and an inertial sensor mechanically coupled with the body. The inertial sensor is configured to monitor the motion of the body and generate a movement signal representative of the body motion. A controller operatively coupled with the inertial sensor controls power usage by at least one or more of the electronic components as a function of the movement signal.

Abstract: In one embodiment, an apparatus includes a package that encompasses at least a first integrated circuit die and a second integrated circuit die. The first integrated circuit die is attached to the package and includes one or more electrical overstress/electrostatic discharge (EOS/ESD) protection circuits. The second integrated circuit die is attached to the package and electrically coupled to the first integrated circuit die such that at least one component of the second integrated circuit die is protected from EOS/ESD by the first integrated circuit die.

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by decimalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value.

Abstract: The sampling rate of a digital signal is reduced by storing a series of partial sums of the digital signal instead of the signal itself, thus reducing the memory size required to perform the sampling-rate reduction.

Abstract: Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.

Abstract: An amplifier with a single-input class-AB output stage comprises an input stage providing a signal to an output stage. The output stage comprises a current-splitting stage having a bias current and providing at least two intermediate output currents, and a drive stage receiving the two intermediate output currents and driving an output signal having a positive side and a negative side.

Abstract: Embodiments of the present invention may include power amplifier architectures and systems for use in wireless communication systems. The systems may include a first circuit path for receiving an input signal and decomposing the signal into two vector signals using an out-phasing generator, modifying the vectors based on predetermined value limit, amplifying the vectors using power amplifiers, and combining the vectors to provide an amplified output. The system may include a second circuit path for generating an estimate of an envelope of the input signal and using the envelope to modulate the voltage supplies of the power amplifiers when amplifying the vector signals. The system may also include a feedback path for sending information regarding the envelope of the input signal into the out-phasing generator, which may modify the vector signals in response thereto.

Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.

Abstract: This disclosure relates to temperature stabilization of at least a portion of an amplifier, such as a logarithmic amplifier, and/or a band gap reference circuit. In one aspect, one or more stages of an amplifier, a heater, and a temperature sensor are included in a semiconductor material and surrounded by thermally insulating sidewalls.

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO and a calibration voltage generation circuit that can generate a calibration voltage for controlling a tuning voltage input of the VCO when the VCO is being coarsely tuned. Additionally, the calibration voltage generation circuit can sense a temperature of the PLL, and can control a voltage level of the calibration voltage to provide compensation based on the sensed temperature. The calibration voltage generation circuit can include a bandgap reference circuit configured to generate a zero-to-absolute-temperature (ZTAT) current and a proportional-to-absolute temperature (PTAT) current, and the calibration voltage can be generated based in part on a difference between the PTAT current and the ZTAT current.

Abstract: Apparatus and methods for multiphase oscillators are provided. In certain implementations, an oscillator system includes a first multiphase oscillator and a second multiphase oscillator that are phase and frequency-locked. Additionally, the first and second multiphase oscillators are phase-locked by an amount of phase shift that provides colocated clock signal phases of relatively wide angular distances, which can be used by the oscillators' amplification circuits. The first and/or second multiphase oscillators include one or more amplification circuits that operate using at least one clock signal phase generated by the first multiphase oscillator and using at least one clock signal phase generated by the second multiphase oscillator.

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.

Abstract: Circuits and method for providing voltage reference circuits that include low drift over time and lower operating voltages are provided. Generally, it is desirable that a reference circuit provide an accurate and precise reference over time. The voltage reference circuits described can provide for good long term stability, operation at lower voltages than prior designs, consistent output voltage with reduced variability due to process changes and mismatches, low noise in the reference voltage, and other advantages.

Abstract: An inductor current emulation circuit for use with a switching converter in which regulating the output voltage includes comparing an output which varies with the difference between the output voltage and a reference voltage with a ‘ramp’ signal which emulates the current in the output inductor. A current sensing circuit produces an output which varies with the current in the switching element that is turned on during the ‘off’ time, an emulated current generator circuit produces the ‘ramp’ signal during both ‘off’ and ‘on’ times, a comparator circuit compares the ‘ramp’ signal with at least one threshold voltage which varies with the sensed current and toggles an output when the ‘ramp’ exceeds the thresholds, and a feedback circuit produces an output which adjusts the ‘ramp’ signal each time the comparator circuit output toggles until the ‘ramp’ signal no longer exceeds the threshold voltages.

Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.

Abstract: Systems and methods can detect a relationship between portions of an analog input signal using a single sensing point, and can provide information about the detected relationship in a digital signal. A system can include an input transconductance stage, a gate circuit driven by a first control signal, a phase-select multiplexer circuit driven by a second control signal, and multiple analog-to-digital converter (ADC) channels. The ADC channels can include respective integrator circuits that receive information from the phase-select multiplexer circuit, and the ADC channels can include comparator circuits coupled to respective outputs of the integrator circuits. The outputs of the comparator circuits can be used as control signals for respective feedback multiplexers, or respective feedback current DACs, that selectively couple reference currents to the respective integrator circuit inputs. The feedback current DACs can be configured to continuously provide information to the respective integrator circuits.