Abstract: A temperature sensing system can include first and second temperature sensing circuits and a digitizing encoder. The first and second temperature sensing circuits can include respective devices with semiconductor junction areas. Temperature information can be determined from one or more characteristic signals measured from the temperature sensing circuits. A feedback circuit can be configured to provide one or more offset signals to the digitizing encoder. The one or more offset signals can correspond to components or characteristics of the first and second temperature sensing circuits. In an example, at least one of the first and second temperature sensing circuits can include an adjustable load circuit for use with the other of the first and second temperature sensing circuits.

Abstract: An apparatus includes a processing unit that divides an overlay buffer into a plurality of macro blocks, draws a graphic primitive object including a plurality of pixels, identifies one of the plurality of macro blocks upon a determination that the plurality of pixels has crossed a boundary of the one of the plurality of macro blocks, and image processes the one of the plurality of macro blocks.

Abstract: An example transconductance circuit is provided in accordance with one embodiment. The transconductance circuit can comprise: an output node; at least one transistor; a variable resistance; and a differential amplifier; wherein the at least one transistor and the variable resistance are in series connection with the output node, an output of the differential amplifier is connected to a control node of the at least one transistor, a first input of the amplifier is responsive to an input signal, and a second input of the amplifier is responsive to a voltage across the variable resistance. Such a circuit may overcome noise problems in transconductance circuits which operate over a wide range of input signals with a fixed resistor in series with the at least one transistor.

Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.

Abstract: Certain example embodiments of the present disclosure can provide a parallelized atomic increment. A vgather instruction returns to a plurality of processing elements the value of a memory location. A vgather_hit instruction returns to a function of the number of “hits” to the memory location. In one embodiment, the function is unity. In another embodiment, the function is the number of hits having an ordinal designation less than or equal to the processing element receiving the return value.

Abstract: A packaged integrated device can include a die attach pad having a top surface and a bottom surface. A plurality of leads physically and electrically separated from the die attach pad can be positioned at least partially around the perimeter of the die attach pad. An integrated device die can be mounted on the top surface of the die attach pad. A package body can cover the integrated device die and at least part of the plurality of leads, and at least a portion of the bottom surface of each of the plurality of leads can be exposed through the package body. A plating layer can cover substantially the entire width of an etched lower portion of the outer end of each lead and at least the exposed portion of the bottom surface of each lead.

Abstract: A line voltage control circuit for use with a multi-string LED drive system which provides a common line voltage for multiple LED strings that are connected to respective current sink circuits at respective junctions. An error amplifier receives the minimum junction voltage and a reference ‘desired junction voltage’ at respective inputs, and a voltage regulator outputs the line voltage in response to a voltage applied to a feedback input. A comparator toggles an output when the maximum junction voltage (Vmax) exceeds a reference limit (Vlimit). A multiplexer receives the error amplifier output and a fixed voltage at respective inputs and provides one of the signals to the regulator's feedback input in response to the comparator output. When Vmax>Vlimit, the fixed voltage is provided to the feedback input and the line voltage is reduced, thereby protecting low voltage current sinks from potentially damaging high voltages.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: The present invention may provide a system including a controller and a plurality of integrated circuits. The controller may control synchronization operations of the system, the controller may include a master timing counter and a controller data interface. Each integrated circuit may include a timing counter and an IC data interface. Further, each integrated circuit may synchronize its respective timing counter based on synchronization command received from the controller via the data interfaces. Hence, the system may provide synchronization between the controller and the integrated circuits without an extraneous designated pin(s) for a designated common time-based signal.

Abstract: A pre-distortion circuit that may introduce a pre-distortion signal in a communication channel by determining a harmonic signal of the signal to be output. One or more image correction signals of the signal to be output may be determined. The one or more image correction signals may be complex conjugate signal variations of the signal to be output. The harmonic signal, the one or more image correction signals and the signal to be output may be combined into a combined output signal. The combined output signal may be transmitted to a digital-to-analog converter. The predistortion circuit may be implemented in a FPGA, an ASIC, a digital-to-analog converter, and/or a separate IC package.

Abstract: The present disclosure provides an attenuator and associated methods of operations. An exemplary attenuator includes an input terminal, an output terminal, a voltage reference terminal, a first attenuation segment coupled with the input terminal and the output terminal, and a second attenuation segment coupled with the first attenuation segment and the voltage reference terminal. The attenuator further includes at least two switches coupled with the input terminal and the output terminal in parallel with the first attenuation segment, where at least some of the at least two switches have an associated voltage control terminal. For example, the attenuator includes a first switch and a second switch coupled with the input terminal and the output terminal in parallel with the first attenuation segment, wherein a first voltage control terminal is coupled with the first switch and a second voltage control terminal is coupled with the second switch.

Abstract: The present disclosure provides for split-path data acquisition chains and associated signal processing methods. An exemplary integrated circuit for providing a split-path data acquisition signal chain includes an input terminal for receiving an analog signal; an output terminal for outputting a digital signal; and at least two frequency circuit paths coupled with the input terminal and the output terminal, wherein the at least two frequency circuit paths are configured to process different frequency components of the analog signal and recombine the processed, different frequency components, thereby providing the digital signal.

Abstract: Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy, and the package lid and the package substrate define a package interior. The package lid includes an interior coating suited to good adhesion with the epoxy, and an exterior coating suited to RF shielding, where the materials of the interior and exterior coatings are different. In one example, the interior lid coating is nickel whereas the exterior lid coating is tin.

Abstract: A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses the property that a power MOSFET has almost a same conductive resistance at a large drain current. Thus, the current limit threshold can be set according to an accurate drain-to-source voltage Vds at a small current sink that is less than a maximum current that ATE is able to provide. An accurate voltage Vds can be measured through Kelvin sensing drain and source pins of the power MOSFET, which are connected to a current sense circuit.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: A switching regulator IC contains both switching regulator circuitry and an inductor and a capacitor connected in parallel to form a resonant circuit having an associated notch filter frequency response arranged such that, when connected to receive the regulated output voltage, the resonant circuit attenuates the ripple component. This is accomplished by matching the resonant notch to the ripple's fundamental frequency, either manually or automatically. In addition, the resonant circuit's inductor and capacitor can act in concert with decoupling capacitors coupled to the load to form a low pass filter which attenuates harmonics of the ripple's fundamental frequency.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: Data-transfer transactions in the read and write directions may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions in the same direction back-to-back for each snapshot.

Abstract: A pre-distortion circuit that may introduce a pre-distortion signal in a communication channel by determining a harmonic signal of the signal to be output. One or more image correction signals of the signal to be output may be determined. The one or more image correction signals may be complex conjugate signal variations of the signal to be output. The harmonic signal, the one or more image correction signals and the signal to be output may be combined into a combined output signal. The combined output signal may be transmitted to a digital-to-analog converter. The predistortion circuit may be implemented in a FPGA, an ASIC, a digital-to-analog converter, and/or a separate IC package.