Abstract: A pre-distortion circuit that may introduce a pre-distortion signal in a communication channel by determining a harmonic signal of the signal to be output. One or more image correction signals of the signal to be output may be determined. The one or more image correction signals may be complex conjugate signal variations of the signal to be output. The harmonic signal, the one or more image correction signals and the signal to be output may be combined into a combined output signal. The combined output signal may be transmitted to a digital-to-analog converter. The predistortion circuit may be implemented in a FPGA, an ASIC, a digital-to-analog converter, and/or a separate IC package.

Abstract: Data-transfer transactions in the read and write directions may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions in the same direction back-to-back for each snapshot.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: Techniques to develop negative impedance circuits that may operate to their power supply rails. The techniques may include generating currents in response to voltage signals presented at respective input terminals of a negative impedance circuit. The voltage signals may be differential signals. The generated currents may be driven through a common impedance within the negative impedance circuit. The currents flowing through the common impedance may be mirrored back to the input terminals of the negative impedance circuit. The negative impedance circuit may be controlled to operate about a common-mode voltage for the circuit.

Abstract: A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.

Abstract: Data-transfer transactions from multiple masters may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions from each master back-to-back.

Abstract: Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes.

Abstract: An electrical circuit includes a photodiode that receives a light signal from a light source and generates a photocurrent signal, a trans-impedance amplifier that amplifies the photocurrent signal and generates a low noise signal, and a high pass filter that converts the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude. The electrical circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The electrical circuit further includes at least one analog-to-digital converter that receives the positive and negative integrated values.

Abstract: A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a pulsed, substantially-random signal into a plurality of channels in the ADC. After the substantially-random signal is injected, a gain correlation value is determined for each channel, which value indicates a degree of correlation between the injected substantially-random signal and an output of the respective channel. The gain correlation values are then compared to determine a degree of mismatch between the channels. At least one of the channels is calibrated as a function of the determined degree of mismatch.

Abstract: A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell.

Abstract: A circuit and a system that uses the circuit for connecting a plurality of input channels to a receiving device. The circuit includes a plurality of DMOS switches, each of which connects a respective one of the input channels to the receiving device in response to a respective control signal. The control signals are referenced to a ground signal. Each input channel includes a common mode voltage that is non-referenced to the ground signal. The circuit also includes a switch driver that generates the control signals such that the input channels are activated one at a time.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the DAC comprises a first and second switching network, the second switching network providing multiple switched paths which compensate for impedance effects of the second string and provides multiple state changes at the output node of the DAC.

Abstract: In an example, there is disclosed herein a digital-to-analog converter (DAC) including a correction circuit for a clock, including a differential clock. Error correction may take place within the DAC core, by means of replica cells that are substantially similar to conversion cells. Rather than contributing their output to the converted signal, the replica cells may be configured to provide a feedback signal to a clock receiver with information for correcting the clock signal. The feedback signal may be operable to correct errors, for example, in duty cycle and crosspoint, as measured at the DAC core.

Abstract: A transformer based isolated bi-directional DC-DC power converter may have signals for controlling power transfer in first and second directions are derived from the same side of the transformer. The converter may include a transformer, a first switching circuit, a second switching circuit, and a controller. In a first mode, the controller controls the first and second switching circuits, and power is transferred from a first side to a second side. In a second mode, the controller controls the first and second switching circuits, and power is transferred from the second side to the first side.

Abstract: Embodiments of the present invention may provide an improved apparatus and method for reducing distortion in analog circuits. A circuit in accordance with the present invention may include a main path comprising an analog circuit with an input impedance, a source impedance representing the impedance of an input network driving the analog circuit, and a cancellation path. The cancellation path may be in parallel to the main path and may generate a cancelling non-linear current to substantially cancel a non-linear current drawn to the input impedance, resulting in a decrease of non-liner current flowing through the source impedance.

Abstract: In one embodiment, a measuring device may comprise two oscillators. The first oscillator may generate a local reference signal in a frequency detector to detect a fundamental frequency of the alternating current (AC). The second oscillator may generate two substantially mutually orthogonal sinusoid signals having the selected frequency. The measuring device further may comprise a first group of multipliers that mixes the two sinusoid signals with a current and a voltage data signal of the AC respectively, a group of low-pass filters for removing high frequency components from the multiplication products, a second group of multipliers for mixing the filtered multiplication products respectively, and a plurality of adders each to sum together a pair of multiplication products of the second group of multipliers.

Abstract: An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.

Abstract: A system and method for testing capacitance of a load circuit connected to an output pin of a driving circuit In one embodiment, the method may comprise driving a voltage at the output pin to a first voltage; a predetermined current to the output pin; comparing the voltage at the output pin to a reference voltage; and when the voltage at the output pin matches the reference voltage, generating an estimate of capacitance present at the output pin based on a number of clock cycles occurring between an onset of a timed voltage change period and a time at which the voltage at the output pin matches the reference voltage.

Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.