Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.

Abstract: A locking/unlocking mechanism for a contactless gesture detection system of a device is described herein. The locking/unlocking mechanism can facilitate automatic locking, manual locking, and/or manual unlocking of the contactless gesture detection system. The contactless gesture detection system can implement the locking/unlocking mechanisms described herein to control a contactless gesture-based user interface state of the device. In various implementations, the controlling can include detecting gestures associated with a user in a contactless space associated with the device; detecting a defined gesture sequence over a defined time period from the detected gestures; and transitioning the device to a contactless gesture-based user interface locked state or a contactless gesture-based user interface unlocked state based on the defined gesture sequence.

Abstract: A sensor polling unit for microprocessor integration comprises a configuration logic block associated with each of a plurality of external sensor devices. Each configuration logic block issues a read command for predetermined sensor data registers of the associated external sensor device via a read trigger supplied by a trigger generator. A global timer based on a microprocessor clock signal supplies a global time value to the trigger generators. A polling state machine is operatively coupled to the configuration logic blocks for receipt of respective read commands, and issues a corresponding read command to the external sensor device through a standardized bi-directional data communication interface connected to the external sensor device. The polling state machine receives register data transmitted by the external sensor device in response to the read command and transmits the received register data to a microprocessor accessible data memory area for storage.

Abstract: A housing for integrated devices that includes an air-release mechanism is disclosed. This is achieved, in various embodiments, by forming a vent hole in a package substrate, and arranging a package lid over the package substrate. The vent hole allows air to be released from within the cavity package, thereby ensuring that the package lid remains stably affixed to the package substrate despite increased temperatures during processing. The vent hole may be sealed upon mounting the package onto a mounting substrate.

Abstract: Apparatus and methods are disclosed related to low-voltage radio transmitters with high spectral purity. One such apparatus includes a baseband path with a predistortion stage, a programmable filter, and an upconverter core. In an embodiment, the programmable filter is placed between the predistortion stage and the upconverter core. In an embodiment, the programmable filter is configured by a controller to reject out-of-band noise introduced at the predistortion stage or earlier.

Abstract: A transmission system may include an oscillator, a serializer, and a driver. The oscillator may generate at least two clock signals. The serializer may modulate a plurality of data streams based upon the at least two clock signals and a plurality of channels of data. The driver may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.

Abstract: The present subject matter discusses, among other things, apparatus and methods for a delay line. In an example, a delay device can include a first node, a plurality of variable capacitor circuits configured to receive a capacitance set point voltage, a current source, a plurality of switches configured to selectively couple a respective variable capacitor of the plurality of variable capacitors to the first node, an input switch configured to receive an input signal and to couple and decouple the current source to the first node responsive to a state of the input signal, and a comparator configured to receive a reference voltage, to receive a voltage from the first node, and to provide an binary output indicative of a comparison between the reference voltage and the voltage from the first node, wherein the binary output is a delayed representation of the input signal.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: Embodiments of the present invention provide a motor-driven mechanical system with a detection system to measure properties of a back channel and derive oscillatory characteristics of the mechanical system. Uses of the detection system may include calculating the resonant frequency of the mechanical system and a threshold drive DTH required to move the mechanical system from the starting mechanical stop position. System manufacturers often do not know the resonant frequency and DTH of their mechanical systems precisely. Therefore, the calculation of the specific mechanical system's resonant frequency and DTH rather than depending on the manufacturer's expected values improves precision in the mechanical system use. The backchannel calculations may be used either to replace or to improve corresponding pre-programmed values.

Abstract: An asynchronous sample rate converter prevents the folding back of a signal in the passband of an input sample rate into the passband of the output sample by adaptively controlling the decimation rate. The ASRC includes an adaptive decimation rate controller that selectably controls a decimation filter based on the ratio of the input sampling rate to the output sampling rate. By adaptively controlling the decimation rate in the ASRC, a significant amount of area and power is saved.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: In an example, a system and method are disclosed for providing a single control law that is operable to regulate both small-signal, steady-state operation, and large-signal transients of a switching regulator. The control law is based on detecting a zero-crossing of capacitor current, and projecting in advance a turning point for either ramping up or ramping down capacitor voltage at a target voltage. Certain embodiments may realize the control function in high-speed analog components, although certain other embodiments may implement the same or a similar control law in a digital controller.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. A control loop is provided to control the Ron of the switching network and provide code dependent control of switches in a DAC switching network.

Abstract: A root-mean-square (RMS) detector includes detection circuitry having as an input a radio frequency signal, target voltage and a set voltage and a RMS signal as an output, and a gain stage within the detection circuitry to produce the RMS signal as an output. The gain stage provides for faster settling times of the detector.

Abstract: A method for aligning an opto-electronic component in an IC die with an optical port is disclosed. This is achieved, in various embodiments, by forming alignment features in the IC die that can mate with complementary alignment features of the optical port. The formation of alignment features can be performed at the wafer level during fabrication of the IC die. An optical signal carrier may be optically coupled to the optical port such that the signal carrier may communicate optically with the opto-electronic component.

Abstract: A method and circuit to perform noise shaped splitting of a digital input signal may include using multiple layers to process the input signal. In the first layer, the most significant bits of the input signal may be distributed to a plurality of branches. Dynamic element matching may be performed using the least significant bits of the input signal. Based on the results of the dynamic element matching, values may be added to the plurality of branches. If there is insufficient data activity, dynamics enhancement may be performed to increase the data activity. The output signals of each of the plurality of branches in the first layer may be provided to a second layer, in which these steps can be repeated on each of the output signals. The outputs of the second layer may be provided to a plurality of three level unit elements.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.

Abstract: An amplifier may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The predistorter may separately and independently generate a predistortion signal component for the in-phase input signal and a predistortion signal component for the quadrature input signal.