Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Abstract: A clock system including a ring oscillator having a plurality of cascaded inverters, each of the cascaded inverters having a pair of inputs coupled to outputs of a respectively adjacent inverter stage and having a pair of outputs coupled to inputs of another respectively adjacent inverter stage, each inverter stage having a common mode control circuit provided therein, and a feedback controller adapted to transmit a control signal to the common mode control circuit of at least one of the inverters.

Abstract: One aspect of this disclosure is an apparatus including an oscillator that includes a secondary LC circuit to increase a tuning range of the oscillator and/or to reduce a phase noise of the oscillator. Another aspect of this disclosure is an apparatus that includes oscillator with a primary LC circuit and a secondary LC circuit. This oscillator can operate in a primary oscillation mode or a secondary oscillation mode, depending on whether oscillation is set by the primary LC circuit or the secondary LC circuit.

Abstract: Apparatus and methods for loss of signal detection are provided. In one embodiment, a detection circuit for monitoring an input includes a small signal boost circuit, a rectifier circuit, a low-pass filter, and one or more comparators. The small signal boost circuit can generate an amplified signal by providing a first amount of gain to an input signal when the input signal is relatively small, but can saturate and provide reduced gain without external gain control adjustment when the input signal does not have a relatively small magnitude. The rectifier circuit can rectify the boosted signal to generate a rectified signal, and the low-pass filter can filter the rectified signal to generate a filtered signal. The one or more comparators can compare the filtered signal to one or more decision threshold voltages to determine the presence or absence of the input signal on the input.

Abstract: Transmitter noise cancellation may be applied on a channel by channel basis to active channels of an incoming radio frequency signal received at a receiver. A noise cancellation filter may be provided for each active channel in a predetermined signal band. Applying noise cancellation on a per active channel basis instead of to the entire receive band may substantially reduce the filtering requirement and number of filter coefficients or taps to save power and reduce manufacturing costs. Channelized transmitter noise cancellers, multi transmitter-receiver cross coupling cancellers, and hybrid full signal band and channelized transmitter noise cancellers are also provided.

Abstract: In an example, there is disclosed a system and method for detecting and correcting error in a quadrature receiver (QR). The QR may include a receiver channel operable to divide a received RF signal into I and Q channels. The receiver channel may include error sources, such as (in sequence) pre-demodulation (PD) error, LO mixer error, and baseband (BB) error. Test tones may be driven on the receiver channel at a plurality of test frequencies, and a quadrature error corrector may be provided to detect error from each source. Upon receiving an RF signal, the quadrature error corrector may apply correction coefficients to correct each source of error in reverse sequence (BB, LO, PD).

Abstract: At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry.

Abstract: An electrical circuit includes a local oscillator configured to generate a first reference signal and a second reference signal having a predetermined phase shift with the first reference signal, an I-channel mixer configured to inject the first reference signal to an incoming signal and generate a first output, a compensation mixer configured to multiply the first output with a constant factor to generate a second output, a first low pass filter configured to approximately attenuate frequencies in the second output to generate a third output, and a first correcting filter configured to filter the third output to generate a fourth output. The first correcting filter is configured to reduce a channel impulse response mismatch between the first low pass filter and a second low pass filter, which is configured to attenuate frequencies in a Q-channel of the incoming signal. In specific embodiments, the phase shift includes 45°.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: Power efficiency is an important design requirement of power amplifiers. To improve power efficiency, a solution proposed in this present disclosure includes an all-digital zero-voltage switching apparatus for directly driving a switching power amplifier through a desired current pulse shape. The apparatus includes a digital engine and a digital-to-analog converter (DAC). The digital engine processes baseband data and generates a digital output. The digital output of the digital engine drives the DAC to generate a digitally controlled current output having that desired current pulse shape. The digitally controlled current output is used to directly drive the switch power amplifier to improve power efficiency. The digitally controlled current output comprising digitally generated current pulses is controlled accurately by the digital engine and the DAC, and thus allows the switching power amplifier to operate optimally with higher power efficiency than conventional power amplifiers.

Abstract: A method and a corresponding device reduce the convergence time of a correlation algorithm that uses random signals injected into an analog-to-digital converter (ADC) as input to the algorithm. The method and device involve, at a processor of a pipelined ADC, injecting a random signal into each of a plurality of stages in the pipeline and obtaining digital values generated in response to the random signals. Noise components of residue signals in the plurality of stages are calculated as a function of the digital values and values of the random signals. The noise components correspond to the random signals.

Abstract: Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.

Abstract: In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated.

Abstract: Embodiments of the present disclosure may provide a dynamic latch circuit with increased speed and that can perform comparisons on low input signals. The dynamic latch circuit may include a first input transistor receiving a first input signal and a second input transistor receiving a second input signal. A cross coupled inverters may be included to provide a first and second output signals based on the sampled input signals from the first and second input transistors. A reset circuit may be included to reset the first and second outputs to a reference voltage. The latch circuit may include an impedance controller coupled in parallel with the first and second input transistors.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the multi-string DAC is configured to use the voltage change at terminals of a first string separately to the voltage drop across a first switching network that couples the first and second strings to provide an analog output in response to a digital input to the DAC.

Abstract: A composite resistor includes a thin film resistor element having a first temperature coefficient of resistance and a metal resistor element having a second temperature coefficient of resistance. A portion of the metal resistor element overlaps a portion of the thin film resistor element such that the portion of the metal resistor element is in thermal communication with the portion of the thin film resistor element to compensate for a resistance drift arising during operation of the composite resistor.

Abstract: A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.

Abstract: Apparatus and methods for estimating a direct current offset in an upconverter are disclosed. Samples of a first signal are received. Values of a compensation signal are retrieved. For example, the compensation signal can be a component in a modified baseband signal, wherein the modified baseband signal is upconverted, downconverted, and filtered to generate the first signal. An estimate of a first DC offset induced by an upconverter is generated based at least partly on at least two selected samples of the first signal and corresponding values of the compensation signal.

Abstract: One example embodiment provides a system, apparatus, and method for using polynomial models in tone calibration for quadrature error correction in I/Q receivers. In one example embodiment, method for calibrating an I/Q receiver is provided and includes receiving a first mismatch parameter indicating a mismatch between I and Q channels of the I/Q receiver; and estimating a second mismatch parameter from the first mismatch parameter using a polynomial model.

Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.