Abstract: A filter may include multiple circuit sub-systems, where one circuit sub-system may have an output connected to an input of another circuit sub-system. Each circuit sub-system may include an amplifier with an output connected to the output of the circuit sub-system. Each circuit sub-system may include a first network connecting an input of the circuit sub-system to a first reference input of the amplifier, and a second network connecting the output of the amplifier to the first reference input of the amplifier. The filter may include a link network connecting the output of one circuit sub-system to an input of another circuit sub-system.

Abstract: Signal flows for data-processing applications may be implemented so as to enable each processing node in the flow when it contains a sufficient amount of input data at its input buffer. In various embodiments, such signal flows can be graphically defined in a GUI tool which, thereafter, auto-generates suitable code for implementing the signal flow.

Abstract: A reference voltage generator circuit may include at least one MOS transistor and at least one bipolar transistor coupled together to provide an electrical path from an input reference potential to an output of the generator circuit. The electrical path may extend through a gate-to-source path of the MOS transistor and further through a base-to-emitter path of the bipolar transistor. The MOS transistor may be biased by a bias current that is proportional to T2·?(T), where T represents absolute temperature and ?(T) represents mobility of a MOS transistor in the bias current generator. Optionally, the reference voltage generator may include N MOS and M multiple bipolar transistors (N?1, M?1), and the output reference voltage may be N*VGS+M*VBE as compared to the input reference potential.

Abstract: A device that supports communication over parallel serial lanes may include an analog circuit domain, a digital circuit domain, a buffer between the analog domain and the digital domain, and an alignment circuit. The buffer may receive data from the digital domain according to a write clock and send out the received data to the analog domain according to a read clock. The alignment circuit may generate control signals to initiate reading from the buffer when the read clock and write clocks are aligned. In one embodiment, the device may be an analog-to-digital converter (ADC) integrated circuit (IC) chip and the buffer may be a FIFO.

Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.

Abstract: Channel estimation for high mobility OFDM channels is achieved by identifying a set of channel path delays from an OFDM symbol stream including carrier data, inter-channel interference noise and channel noise; determining the average channel impulse response for the identified set of channel path delays in each symbol; generating a path delay curvature for each channel path delay in each symbol based on stored average channel impulse responses for the identified channel path delays; estimating the carrier data in the symbols in the OFDM symbol stream in the presence of inter-channel interference noise and channel noise from the OFDM symbol steam and the average impulse responses for the identified channel path delays; reconstructing the inter-channel interference noise in response to the path delay curvature, the identified set of channel path delays and estimated carrier data to produce a symbol stream of carrier data and channel noise with suppressed inter-channel interference noise.

Abstract: Systems and methods for capacitance multiplication using one charge pump for a phase lock loop employ a digital controlled loop filter that operates in a time division mode. Embodiments of the loop filter block the current from the charge pump according to the digital control, such that the charge pump cannot charge or discharge the integral capacitor when the digital control is enabled. Because at least a portion of the current is blocked, it takes more time for the charge pump to charge or discharge the capacitor to a certain level. The capacitor then appears to be larger than its actual value with respect to operation of the phase lock loop.

Abstract: Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation.

Abstract: Embodiments of the present invention may provide a multi-string DAC with leakage current cancellation. A leakage cancellation circuit may be coupled to output node(s) of the—multi-string DAC. The leakage cancellation circuit may replicate leakage current present at the coupled output node(s) and generate a corresponding complementary signal, a leakage cancellation signal. The leakage cancellation signal may be injected into the coupled output node(s) to cancel (or reduce) the net impact of the leakage current.

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.

Abstract: A decoder control makes use of controllable transfer gates, which effectively implement selectors, to implement required timing offsets for codes that have particular structure. For instance, such timing offsets are effective for LDPC codes with block off-diagonal structure, for instance, as described in the co-pending application. In some implementations, the memory architecture is formed of cells where each cell includes not only a storage element, by also control logic that combines a select signal and the write versus read signal. By co-locating this control logic in each memory cell, control logic and its associated signal distribution is reduced, thereby reducing circuit area and power consumption.

Abstract: In general, in one embodiment, low-light noise is removed from an image by separately filtering luma and chroma components of the image, by adaptively filtering the image based at least in part on a Gaussian distribution of the image, and/or by dividing the image into separate regions and filtering each region separately.

Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, an apparatus includes an invertible sine shaping filter configured to receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal. The invertible sine-shaping filter is further configured to filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals. The invertible sine-shaping filter is further configured to selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal. The apparatus further includes a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal. The in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.

Abstract: A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.

Abstract: A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs.

Abstract: A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.

Abstract: Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate having a mounting segment and a first wing segment extending from the mounting segment. The first wing segment may be folded around an edge of the stiffener. A sensor die may be mounted on the mounting segment of the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die.

Abstract: Previously available analog domain decimation techniques are limited to simple equally-weighted averaging of photosite outputs. Decimation of a Bayer pattern image by an even-factor, such as by two or six, using simple equally-weighted averaging of photosite outputs in the analog domain results in effective sampling locations that are unevenly spaced apart. Standard interpolation of the unevenly spaced effective sampling locations generates image artifacts that reduce the quality of the reconstructed image in the smaller format because standard interpolation methods assume that the effective sampling locations are evenly spaced. Implementations of systems, methods and apparatus disclosed herein aim to produce substantially evenly spaced effective sampling locations in the analog domain.

Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.