Abstract: An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements.

Abstract: An amplifier system may include a power stage having inputs for three different supply voltages and an output for coupling to a load, a controller to generate control signals to the power stage that cause the power stage to vary an output voltage applied to the load among more than three distinct voltage levels, a monitor to provide a first control signal to the controller based on an input voltage signal, and a feedback system to provide a second control signal to the controller based on comparison of the output voltage and the input signal.

Abstract: A digital audio interface may include two signal inputs to transmit audio data. A first signal line may carry digital serial audio data. The second signal line may carry a word clock signal to differentiate the serial audio data transmitted over the first signal line. In the case of stereo audio data, the word clock signal may correspond to a left-right clock signal and may differentiate audio data intended for a right channel from that intended for a left channel. The audio data may also be differentiated differently depending on the configuration, such as in the case that the transmitted audio data include audio for more than two channels. The word clock signal may be scaled to regenerate a bit clock signal used to encode the serial audio data over the first signal line. The encoding bit clock signal need not be transmitted.

Abstract: A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset.

Abstract: Compensation methods and systems for voltage-feedback amplifiers provide improved dynamic performance (i.e., increased bandwidth and the elimination or alleviation of a slew limitation) at various gains by self-adaptively changing the Miller effect with respect to the gain setting.

Abstract: A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: A control aperture for an IR sensor includes a die; an IR sensor disposed on the die and an IR opaque aperture layer on the die having an IR transmissive aperture aligned with the IR sensor for controlling the field of view and focus of the IR sensor.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A multi-channel circuit includes a first-channel circuit configured to receive a digital input and a second-channel output voltage, and to generate a first-channel output voltage as a function of the received digital input and second-channel output voltage.

Abstract: An OVP system which includes a plurality of OVP circuits coupled to respective parallel-connected switching power supplies. Each OVP circuit comprises a bus voltage overvoltage detection circuit having a first output which toggles when the voltage on the common power bus exceeds a reference voltage, a modulation flag detection circuit which receives a value that varies with a parameter associated with the PWM or PFM drive signals generated for the switching power supply to which the OVP circuit is coupled and has a second output which toggles when the parameter value exceeds a reference parameter value, logic circuitry which toggles an output when both the first and second outputs toggle, and an overvoltage response circuit which initiates a course of action such as latching or shutting down the switching power supply to which the OVP circuit is coupled when the logic circuitry's output toggles.

Abstract: Embodiments of the present invention provide a motor-driven mechanical system with a detection system to measure properties of a back channel and derive oscillatory characteristics of the mechanical system. Uses of the detection system may include calculating the resonant frequency of the mechanical system and a threshold drive DTH required to move the mechanical system from the starting mechanical stop position. System manufacturers often do not know the resonant frequency and DTH of their mechanical systems precisely. Therefore, the calculation of the specific mechanical system's resonant frequency and DTH rather than depending on the manufacturer's expected values improves precision in the mechanical system use. The backchannel calculations may be used either to replace or to improve corresponding pre-programmed values.

Abstract: Apparatus and methods for frequency compensation of an amplifier are provided. In one embodiment, an integrated circuit (IC) includes an amplifier configured to amplify an input signal to generate an output signal. The IC further includes an output pad configured to receive an output signal from the amplifier and a control pad for controlling the closed-loop bandwidth of the amplifier. A compensation capacitor is electrically connected between an input of the inverting amplification block and an output of the inverting amplification block, and a switchable capacitor is electrically connected between the input of the inverting amplification block and the control pad. The control pad can be electrically connected to a DC voltage source or to the output pad to control the amplifier's closed-loop bandwidth.

Abstract: A method for correcting digital gain error for a digital code includes receiving the digital code, generating a random number, adding a first dither to the digital code, in which a magnitude of the first dither is determined based on the random number, performing an operation on the digital code including the added dither with a factor to generate a scaled digital code, and subtracting a second dither corresponding to the first dither from the scaled digital code.

Abstract: Apparatus and methods are also disclosed related to tuning a quality factor of an LC circuit. In some implementations, the LC circuit can be embodied in a low-noise amplifier (LNA). A quality factor adjustment circuit can increase and/or decrease conductance across the LC circuit. This can stabilize a parasitic resistance in parallel with the LC circuit. In this way, a gain of the LC circuit can be stabilized.

Abstract: A sigma delta modulator may include a loop filter and an adder configured to accept an output of the loop filter and a dither input signal. The adder may be further configured to combine the output of the loop filter and the dither input signal into a combined output signal. The sigma delta modulator may further include a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal. The sigma delta modulator may further include a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal.

Abstract: Methods and resulting devices are disclosed related to attaching a die to a leadframe. One such method includes initially bonding a carrier pad which is pre-coated with a thermosetting first adhesive to the leadframe. The carrier pad can be electrically non-conductive. The first adhesive can be raised to its thermosetting cure temperature by heating the leadframe to a temperature just above the thermosetting cure temperature of the first adhesive. A thermosetting second adhesive which is liquid at room temperature can be applied to a second major surface of the carrier pad, and the die can be placed on the second adhesive and aligned with the leadframe. The second adhesive can be raised to its thermosetting cure temperature to bond the die to the carrier pad, and in turn form a bonded assembly.

Abstract: Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.