Abstract: A detector circuit can include an integrator having an amplifier, a first feedback capacitor connected between an input and output of the amplifier, one or more additional feedback capacitors connected by at least one switch between the input and output of the amplifier, and a shunt capacitor connected to the output of the amplifier. The shunt capacitor can be selected to have a capacitance value greater than that of a minimum but less than that of a maximum feedback capacitance. The detector circuit can further include a sampling circuit having a sampling capacitor connected to the output of the integrator amplifier through at least one switch, wherein the sampling capacitor is separate from the shunt capacitor. A computed tomography imaging apparatus can include the detector circuit.

Abstract: A system and method provide for a radio transmitter with digital predistortion. The radio transmitter includes a high output power narrowband upconverter and a low output power wideband upconverter. In a stage of the radio transmitter, digital predistortion is applied to transmit data by setting digital coefficients by a digital predistortion algorithm, resulting in a predistortion signal. A predistortion signal is separated into a narrowband component and a wideband component, where the narrowband component corresponds to a desired traffic signal and the wideband component corresponds to a digital predistortion signal reflecting separated digital predistortion correction products. The narrowband upconverter provides a transmission path for a desired traffic signal or transmit data (the narrowband component of the digital predistortion signal), while the wideband upconverter provides a transmission path for the wideband component representing digital predistortion correction products.

Abstract: A clock generator is disclosed for use with an oscillator device. The clock generator may include a signal conditioning pre-filter and a comparator. The signal conditioner may have an input for a signal from the oscillator device, and may include a high pass filter component and a low pass filter component. The high pass filter component may pass amplitude and frequency components of the input oscillator signal but reject a common mode component of the oscillator signal. Instead, the high pass filter component further may generate its own common mode component locally over which the high frequency components are superimposed. The low pass filter component may generate a second output signal that represents the locally-generated common mode component of the first output signal. The clock generator may have a comparator as an input stage which is coupled to first and second outputs of the filter structure.

Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.

Abstract: An inductor current emulation circuit for use with a switching converter in which regulating the output voltage includes comparing an output which varies with the difference between the output voltage and a reference voltage with a ‘ramp’ signal which emulates the current in the output inductor. A current sensing circuit produces an output which varies with the current in the switching element that is turned on during the ‘off’ time, an emulated current generator circuit produces the ‘ramp’ signal during both ‘off’ and ‘on’ times, a comparator circuit compares the ‘ramp’ signal with at least one threshold voltage which varies with the sensed current and toggles an output when the ‘ramp’ exceeds the thresholds, and a feedback circuit produces an output which adjusts the ‘ramp’ signal each time the comparator circuit output toggles until the ‘ramp’ signal no longer exceeds the threshold voltages.

Abstract: A system and method for removing noise from images are disclosed herein. An exemplary system includes an edge-detection-based adaptive filter that identifies edge pixels and non-edge pixels in an image and selects a filtering technique for at least one non-edge pixel based on a comparison of the at least one non-edge pixel to a neighboring pixel region, wherein such comparison indicates whether the at least one non-edge pixel is a result of low-light noise.

Abstract: A microelectronic circuit having at least one component adjacent a carrier which is not a semiconductor or sapphire.

Abstract: Apparatus and methods are disclosed related to trimming an input offset current of an amplifier. One such apparatus can include auxiliary bipolar transistors connected in parallel with bases of respective bipolar transistors of an input stage of an amplifier. The auxiliary bipolar transistors can be biased such that the base currents of the auxiliary bipolar transistors compensate for a mismatch in base currents of the bipolar transistors of the input stage of an amplifier. The offset current at an input of an amplifier can be reduced independent of an offset voltage at the input of the amplifier.

Abstract: A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.

Abstract: An infrared sensor, comprising at least one pixel comprising a first sensor and a second sensor, wherein the first and second sensors are dissimilar.

Abstract: A method of forming a capped die forms a cap wafer having a top side and a bottom side. The bottom side is formed with 1) a plurality of device cavities having a first depth, and 2) a plurality of second cavities that each have a greater depth than the first depth. At least some of the plurality of second cavities each generally circumscribe at least one of the device cavities. The method then secures the cap wafer to a device wafer in a manner that causes a plurality of the device cavities each to circumscribe at least one of circuitry and structure on the device wafer. Next, the method removes at least a portion of the top side of the cap wafer to expose the second cavities. This forms a plurality of caps that each protect the noted circuitry and structure.

Abstract: An overvoltage protection devices operable to provide protection against overvoltage events of positive and negative polarity, comprising: an N P N semiconductor structure defining: a first N-type region; a first P-type region; and a second N-type region; wherein one of the first or second N-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second N-type regions is connected to a reference, and wherein a field plate is in electrical contact with the first P-type region, and the field plate overlaps with but is isolated from portions of the first and second N type regions.

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract: A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell.

Abstract: One embodiment relates to an apparatus configured to cancel charge injected on a node of a differential pair of nodes. A dummy circuit element can inject charge on an inverted node to cancel charge injected on a non-inverted node by a switch when the switch is switched off. In addition, another dummy circuit element can inject charge on the non-inverted node to cancel charge injected on the inverted node by another switch when the other switch is switched off. These dummy circuits elements can be cross-coupled.

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract: Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator.

Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.

Abstract: The present disclosure provides an amplifier and associated methods of operations. An exemplary amplifier an input terminal; an output terminal; a first virtual ground node; a second virtual ground node; an operational amplifier coupled with the input terminal and the output terminal; a resistive input section coupled with an input of the operational amplifier; and a resistive feedback section coupled with an output of the operational amplifier. The resistive input section includes a fixed input resistor coupled with the input terminal and the first virtual ground node, and a switchable input resistor segment coupled with the fixed input resistor in parallel. The resistive feedback section includes a fixed feedback resistor coupled with the output terminal and the first virtual ground node, and a switchable feedback resistor segment coupled with the fixed feedback resistor in parallel.

Abstract: An apparatus for transceiver signal isolation and voltage clamp from transient electrical events includes a bi-directional protection device comprising a bipolar PNPNP device assembly, a first parasitic PNPN device assembly, and a second parasitic PNPN device assembly. The bipolar PNPNP device assembly includes an NPN bi-directional bipolar transistor, a first PNP bipolar transistor, and a second PNP bipolar transistor, and is configured to receive a transient voltage signal through first and second pads. The first and second pads are electrically connected to the PNPNP device assembly through emitters of the first and second PNP bipolar transistors. The bipolar PNPNP device assembly is electrically connected to a first parasitic PNPN device assembly comprising a parasitic PNP bipolar transistor and a first parasitic NPN bipolar transistor.