Abstract: A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification

Abstract: An electronic chip has a data input for receiving an input digital data signal with a data frequency, a plurality of switches, and a logic circuit operatively coupled with both the plurality of switches and the data input. The logic circuit controls the switches to be in one of a DAC mode or a mixer mode. The DAC mode causes the switches to convert the input digital data signal into a DAC analog signal having about the data frequency. The mixer mode, however, causes the switches to convert the input digital data signal into a mixed analog signal having a mixer frequency that is higher than the data frequency.

Abstract: A sensor element is capped by bonding or otherwise forming a cap on a sensor element. The sensor may be hermetically sealed by using a hermetic cap and hermetic bonding material or by applying a hermetic coating. The sensor may be filled with a gas at an elevated pressure. The sensor may alternatively or additionally be filled with a special gas, such as a gas having a density-to-viscosity ratio above approximately 0.2.

Abstract: Real-time clock calibration is accomplished by generating a fast clock signal and a slow clock signal from an uncompensated clock signal; selectively, momentarily, replacing the uncompensated clock signal with the fast and slow clock signal to generate a compensated clock signal; generating from the compensated clock signal a calibration strobe and window trigger; responding to the window trigger to detect any uncompensated clock signal frequency error and responding to the calibration strobe to selectively, momentarily, replace the uncompensated clock signal with the fast or slow clock signal to reduce the clock signal frequency error.

Abstract: An embodiment of a voltage-measuring circuit includes: a first resistor connected to a first measurement node; a second resistor connected to the first resistor and a second measurement node; a configuration switch configured to, in response to a control signal, selectively interconnect the first and second resistors, during enable and disable phases of the control signal respectively, into and out of either a parallel or a series configuration; and a control and measurement circuit configured to provide the control signal, receive a first measurement voltage from the first and second measurement nodes during the enable phase, and receive a second measurement voltage from the first and second measurement nodes during the disable phase.

Abstract: An embodiment of a multi-path, multi-oxide-thickness amplifier circuit includes a first amplifier having at least one thin-oxide output transistor, and a second amplifier having at least one thick-oxide output transistor. The first and second amplifiers are connected in parallel with each other between an input terminal and an output terminal of the amplifier circuit. The thin-oxide output transistor has a gate-oxide layer thickness that is less than a gate-oxide layer thickness of the thick-oxide output transistor.

Abstract: A method of bonding two members includes forming a metal pad on a first member and a silicon pad on the second member, and coupling the pads at a temperature and pressure that will not damage features of the members, such as integrated circuitry or MEMS devices, but is sufficient to form a silicide bond. In various embodiments, the metal may be nickel and the silicon may be polysilicon.

Abstract: An exemplary negative impedance converting circuit for functioning as a voltage buffer and/or negating the impedance of a connected load. The negative impedance converting circuit includes inputs, outputs, a first transconductance stage and a second transconductance stage. The transconductance gain value of the first transconductance stage is greater than a transconductance gain value of the second transconductance stage. Exemplary embodiments of a reference voltage buffer using the negative impedance converting circuit are also described.

Abstract: A sub-pixel interpolation technique is provided for motion vector estimation during video coding. In one embodiment, this is accomplished by interpolating adjacent pixels at fractional horizontal, vertical, and diagonal locations in a macroblock of (M×N) pixels, such that there are no overlapping interpolations, to generate values for sub-pixels associated with the macroblock of (M×N) pixels.

Abstract: A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.

Abstract: Filter system embodiments are provided for realizing interpolation and decimation processes with interleaved filter structures. These interleaved structures enable the systems to obtain output data rates that exceed the highest operation rates of the system components.

Abstract: A device and method for correlation-based background calibration of pipelined converters with a reduced power penalty. A pipelined analog-to-digital converter (ADC) utilizes a random or pseudorandom signal to reduce the quantization error of subconverting stages. Stages within the ADC comprise an injection circuit having a plurality of capacitive branches in parallel. Less than all of the branches can function during a given clock cycle of the ADC. This allows a subconverting stage within the ADC to be accurately trimmed before operation using a large amplitude signal. At the same time, the capability to inject smaller amplitude random or pseudorandom signals into the subconverting stage during operation is maintained, saving valuable dynamic range and power. The various capacitive branches are cycled through either randomly or in sequence such that the quantizer manifests the same average gain error over time for which the quantizer was initially trimmed.

Abstract: A vehicle engine sound simulator includes a crossfade sample playback engine which produces an output waveform comprising at least two constituent waveforms which are transposed up and down in frequency with RPM. The playback engine's output waveform is provided to at least one digital signal processing (DSP) circuit, which processes the output with a function that varies with the rate of change of RPM, an external load value, and/or a combination of both to produce the simulator's output. The crossfade sample playback engine is arranged to crossfade between at least 2 wave samples as RPM changes. Wave samples from additional wave banks associated with different load states can also be mixed into the playback engine's output waveform. The DSP circuit can include both nonlinear and linear processing sections in various combinations.

Abstract: A low voltage shutdown circuit comprises an input node for receiving a voltage Vin to be monitored, first and second voltage-to-current (V to I) converters arranged to receive Vin at respective inputs and to convert Vin to currents I1 and I2 at respective outputs, and a current comparison circuit arranged to produce an output which is in a first state when I1<I2 and in a second state when I1>I2. The V to I converters have respective voltage-to-current transfer functions which intersect at a non-zero threshold voltage Vth, such that the current comparison circuit output toggles when Vin<Vth. This output can be used as needed to, for example, trigger the shut down of other circuitry.

Abstract: An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current.

Abstract: The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial.

Abstract: A system for verifying the identification of a device. A codec is configured to measure at least one electrical characteristic of a device connected to a jack and to identify the device based on the measured electrical characteristic. An updateable database is populated with the electrical characteristic of at least one device whose electrical characteristic was measured by the codec but not correctly identified by the codec and a software routine is responsive to the measured electrical characteristic and configured to adjust the codec's identification of the device based on the electrical characteristic stored in the database to correctly identify the device.

Abstract: A semiconductor device interconnection contact and fabrication method comprises fabricating one or more active devices on a semiconductor substrate. A diffusion barrier layer is deposited over the devices, followed by an Al-based metallization layer. The diffusion barrier and metallization layers are masked and etched to define interconnection traces. Mask and etch steps are then performed to remove interconnection trace metallization that is in close proximity to the active device regions, while leaving the traces' diffusion barrier layer intact to provide conductive paths to the devices, thereby reducing metallization-induced mechanical stress which might otherwise cause device instability.

Abstract: A phase detector includes a first clock driver comprising a first LC tank. The first clock driver provides a strobe to a plurality of flip-flops associated with sampled data being received by the phase detector. The second clock driver includes a second LC tank. The second clock driver provides a strobe to a plurality of flip-flops associated with sampling the phase error of the phase detector. The first and second LC tanks have different adjustable center frequencies and experience a programmable delay between the outputs of the first and second clock drivers so as to determine the data sampling phase of the phase detector.

Abstract: A system for converting digital signals into analog signals using sigma-delta modulation and includes a signed thermometer encoder for converting a plurality of signed binary data received at the encoder into a plurality of signed thermometer data and a rotational dynamic element matching (DEM) arrangement for receiving the plurality of signed binary data and the plurality of signed thermometer data. The rotational DEM arrangement further includes a first barrel shifter for receiving a positive thermometer data at a cycle, the first barrel shifter having a first pointer indicating a starting position of next positive thermometer data, and a second barrel shifter for receiving a negative thermometer data at a cycle, the second shifter having a second pointer indicating a starting position of next negative thermometer data, wherein the first pointer is circularly shifted as a function of positive binary data and the second pointer is circularly shifted as a function of negative binary data.