Abstract: A micro-machined switching system for equalizing an electrical property, such as charge due to parasitic capacitance formed at an input and an output of a micro-machined switching device. The micro-machined switching device may be a MEMS relay or a MEMS switch. In addition to the micro-machined switching device, the switching system also includes a balancing module for equalizing the electrical property between the input and the output of the micro-machined switching device. In certain embodiments, the balancing module includes a switch operable in a first state causing charge due to the parasitic capacitance on the input and the output of the micro-machined switching device to substantially balance. The switch is also operable in a second state wherein parasitic capacitance can separately accumulate at the input and the output of the micro-machined switching device.

Abstract: Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processor, the first jump instruction referencing a pointer to a first target address in the memory table, the processor executing the first jump instruction by jumping to the first target address and modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction. The execution of the first jump instruction may include prefetching at least one future target address from the memory table and writing the future target address in a local memory. The second target address may be accessed in the local memory in response to detection of the second jump instruction.

Abstract: A switching power converter with a controlled startup mechanism includes a switching stage which provides a voltage Vout at an output node in response to a switching control signal, with the output node adapted for connection to a non-linear load. A feedback network compares a signal which varies with the current conducted by the load (Iload) with a reference signal, and provides the switching control signal so as to maintain Iload at a desired value. A capacitor connected to the output node provides a current Ic to the feedback network which varies with dVout/dt. The feedback network is arranged to limit dVout/dt in response to current Ic when Iload is substantially zero. In this way, large inrush currents or damage that might otherwise occur during startup are avoided.

Abstract: A digital waveform synthesiser (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesiser (10) which produces a synthesised output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating

Abstract: Compensation for an RF detector includes components having different order temperature functions. The components are combined and may be adjusted by various numbers of user-accessible terminals to provide individual adjustment for factors such as operating frequency. In some embodiments, first and second-order temperature functions are generated independently and combined to provide a polynomial function of temperature with coefficients that may be adjusted. In other embodiments, the outputs of the function generators may be more complex functions of temperature with various adjustable parameters.

Abstract: A device under test pogo pin type contactor features an active head and an electronic component associated with the active head. A tip is spaced from the active head and a biasing device is between the active head and the tip for biasing the active head against a device under test.

Abstract: Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity.

Abstract: Simultaneously decoding one or more variable length code symbols including storing in a bit FIFO at least a portion of a variable length coded bit stream; storing a succession of extracted bit fields of predetermined bit length from the variable length coded bit stream in the bit FIFO; defining at least one inspection field in the extracted bit field, each inspection field identifying at least one variable length code symbol; and storing in look-up table a decode value uniquely addressable by each bit combination of the inspection field for reading out the one or more decode values corresponding to the unique address defined by the inspection field.

Abstract: A method of estimating a change of a variable over a measurement window, including the steps of taking multiple samples of the variable during the measurement window, defining a weight to be associated with each sample, the weight varying as a function of position of the sample within the measurement window, processing the samples taking account of their weight to form an estimate of the change in the variable.

Abstract: One or more micromachined (MEMS) switches switch attenuators, such as resistors, into or out of a signal path, such as of a test instrument. The MEMS switches can be fabricated on the same substrate as the attenuators, or the switches or attenuators can be mounted on the same substrate as the others are fabricated. An instrument probe includes attenuators and MEMS switches that are controlled by the instrument and/or by a control circuit in the probe. Optionally, the probe includes reactive elements, such as capacitors, and MEMS switches to compensate for electrical characteristics of the probe and/or probe lead, and the probe or a test instrument automatically sets the MEMS switches to connect appropriate ones of the reactive elements to a signal path within the probe.

Abstract: An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.

Abstract: Disclosed are apparatus and methods for electronic signal conversion in which a power level of the signal is used to adjust the bias current of a converter.

Abstract: A side-ported MEMS microphone package defines an acoustic path from a side of the package substrate to a microphone die disposed within a chamber defined by the substrate and a lid attached to the substrate. Optionally or alternatively, a circuit board, to which the microphone package is mounted, may define an acoustic path from an edge of the circuit board to a location under the microphone package, adjacent a bottom port on the microphone package. In either case, the acoustic path may be a hollow passage through at least a portion of the substrate or the circuit board. The passage may be defined by holes, channels, notches, etc. defined in each of several layers of a laminated substrate or circuit board, or the passage may be defined by holes drilled, molded or otherwise formed in a solid or laminated substrate or circuit board.

Abstract: Embodiments of the present invention provide an apparatus and control method for an analog front end (AFE) amplifier for controlling DC restore operations. According to the exemplary method, a first input stage of the AFE is controlled to operate as a continuous time amplifier that has high input impedance and draws substantially no input leakage current for a first predetermined area of an imaging sensor image array. The first input stage is controlled to operate as a sample and hold amplifier with DC restore functionality for a second predetermined area of the imaging sensor image array. According to an embodiment, the AFE input stage operates as a continuous time amplifier when reading pixels from the sensor's active image array but operates as a sample and hold amplifier with DC restore when reading pixels from the image array that correspond to so-called ‘black-level’ pixels or pixels that otherwise fall outside the sensor's active image field.

Abstract: Accelerating processing of a non-sequential instruction stream on a processor with multiple compute units by broadcasting to a plurality of compute units a generic instruction stream derived from a sequence of instructions; the generic instruction stream including an index section and a compute section; applying the index section to localized data stored in each compute unit to select one of a plurality of stored local parameter sets; and applying in each compute unit the selected set of parameters to the local data according to the compute section to produce each compute unit's localized solution to the generic instruction.

Abstract: An integrated energy metering system having an energy meter including a voltage ADC for sensing voltage, a current ADC for sensing current, a microcontroller; a first memory device for storing program data for the energy meter; and a plurality of circuit blocks; a voltage monitor for monitoring a primary power supply; a power supply switch circuit for selectively applying one of the primary and auxiliary power supplies to the energy meter; and a system controller responsive to the voltage monitor for operating the switch circuit to apply the auxiliary power supply when the primary power supply voltage decreases below a predetermined level and gating the power to a first class of circuit blocks in the energy meter and applying power continuously to a second class of circuit blocks.

Abstract: An amplifier front-end comprises an input node for receiving a common-mode voltage Vcm, a differential transistor pair having first and second inputs and outputs, a capacitor, a reference voltage Vref, an error correction circuit, and a switching network. The switching network charges the capacitor to Vref; couples the capacitor to the differential pair's first input and couples Vref to the pair's second input such that the voltage at both inputs is ˜Vref; and couples the input node to the capacitor's other terminal such that the voltage at the first input is level-shifted to ˜(Vcm+Vref). The error correction circuit—typically an auto-zero circuit—is coupled to the differential pair's outputs and arranged to reduce charge injection error and kT/C noise components that would otherwise be present in the outputs due to the level shift.

Abstract: A multi-branch frequency translation system converts a plurality of independent input clocks to a common frequency. One of the converted clock signals is selected as a dominant clock. The remaining converted clock signals are edge-synchronized with the dominant clock. When the system selects another converted clock signal for use as the dominant clock, the newly selected signal already is edge-synchronized with the dominant clock and, therefore, switchover losses can be avoided. The dominant clock can be subject of further frequency translation processes and output from the system.