Abstract: A phase locked loop (PLL) based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The PLL is configured as an all digital PLL and includes a bang-bang phase frequency detector, digital loop filter, and digitally-controlled oscillator. The frequency translator is located in either the reference clock path for division or the PLL feedback loop path for multiplication. The SDM produces a predictable noise characteristic set with known stochastic properties which can be used to smooth any discontinuity in the bang-bang phase frequency detector. The predictable noise of the SDM will produce a dithering delay that eliminates any hard discontinuities. This allows for a bang-bang phase frequency detector based digital PLL.

Abstract: A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.

Abstract: AC-coupled equivalent series resistance (ESR) is introduced into a control circuit to provide additional stability in the feedback control loop. A sub-circuit emulates the effect of a higher value ESR in the output capacitor. The additional ESR in the feedback control loop inserts a zero into the transfer function that describes the circuit response at a desired frequency. The added zero compensates for the effects of unwanted or unavoidable poles in the transfer function, allowing for a greater range of input signal frequencies.

Abstract: A thin film resistor (5) of an integrated circuit comprises an elongate resistive film (7) extending between electrical contact pads (10,11). A low impedance element (20) overlays and is electrically coupled to a portion of the resistive film (7) in an intermediate portion (22) thereof adjacent a second side edge (17) of the resistive film (7) for conducting current in parallel with the intermediate portion (22), and for reducing current density in the intermediate portion (22). First and second transverse edges (28,29) formed by spaced apart first and second slots (26,27) which extend from a first side edge (16) into the resistive film (7) define with a first side edge (16) of the resistive film (7) and the low impedance element (20) first and second trimmable areas (30,31) in the intermediate portion (22).

Abstract: The invention provides a sensor array having a plurality of sensor elements formed in a first substrate and having a plurality of die temperature sensors located thereabout. Each of the die temperature sensors are configured to provide an output related to the temperature of the die on which they are located, the sensor elements providing an output indicative of the intensity of radiation incident thereon.

Abstract: Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal.

Abstract: A logic signal isolator including a micro-transformer with a primary winding and a secondary winding. A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at least a first amplitude signal is supplied to the primary winding and, in response to a second type of edge in the logic signal, a second different amplitude signal is supplied to the primary winding. A receiver circuit receives corresponding first amplitude and second amplitude signals from the secondary winding and reconstructs the received logic input signal from the received signals.

Abstract: Programmable-gain amplifier systems are provided that are particularly suited for reducing degrading audio effects such as zipper noise. In one embodiment, these systems switchably couple an electronic potentiometer between an amplifier's inverting input terminal and interleaved tap points along a resistor that is coupled to the amplifier's output terminal. This arrangement introduces a number of fine gain steps between the gain steps that are realized with adjacent ones of the interleaved tap points to substantially reduce or eliminate zipper noise in a audio system that processes the system's output signal. The interleaved tap points facilitate efficient operation of the potentiometer during gain changes. They also permit the potentiometer to be effectively bypassed between gain changes so that distortion effects are substantially eliminated.

Abstract: A method of operating a circuit for processing a digital signal is disclosed. The circuit includes various circuit stages having respective enabled states. A present signal path is established which includes circuit stages in their respective enabled states. Power is disabled to selected circuit stages not used in the present signal path so as to minimize power consumption in the disabled circuit stages. A data signal is then processed through the circuit stages in the present signal path. Before a next signal path is needed, power is re-enabled to selected disabled circuit stages in the next signal path to allow the enabled circuit stages to approach their respective enabled states. Then the next signal path can be established including the enabled circuit stages in their respective enabled states. The data signal can then be processed through the circuit stages in the next signal path.

Abstract: A method and system for determining camera positioning information from an accelerometer mounted on a camera. The accelerometer measures the orientation of the camera with respect to gravity. Orientation measurement allows user interface information to be displayed in a “right side up” orientation on a viewfinder for any camera orientation. Alternatively, an artificial horizon indicator may be displayed in the viewfinder. The accelerometer may also measure camera movement. Camera movement information together with camera orientation can be used to determine camera usage. Additionally, camera movement information can be used to determine a minimum shutter speed for a sharp picture.

Abstract: A method of producing a MEMS device provides an apparatus having structure on a first layer that is proximate to a substrate. The apparatus has a space proximate to the structure. The method adds doped material to the space. The doped material dopes at least a portion of the first layer.

Abstract: A capped wafer includes a device wafer and an opposing cap wafer with an annular glass frit disposed between the device wafer and the cap wafer. The glass frit and the opposing wafers define a sealed volume that encloses the capped devices, and the glass frit may support the wafer cap during removal of excess wafer cap material from the capped wafer. A method of fabricating a capped wafer includes fabricating an annular intermediate layer between a device wafer and a cap wafer. In an alternate embodiment, a plurality of unsingulated dice each contains bond pads along a single edge and are arranged on a device wafer in an alternating order so that the bond pads of a first die are adjacent to the bond pads of a second die.

Abstract: A pseudo-differential active RC integrator is described. The pseudo-differential active RC integrator includes a common-mode feedback sub-circuit to control the common-mode output signal of the integrator. The common-mode feedback subcircuit may be coupled to one or more virtual ground nodes of the pseudo-differential active RC integrator, and may include one or more transconductors.

Abstract: A low noise voltage reference circuit is described. The reference circuit utilizes a bandgap reference component and may include at least one of a current shunt or filter to reduce high and low noise contributions to the output. Further modifications may include a curvature correction component.

Abstract: This invention further features a method of apportioning channels in a programmable multi-source, multi-destination system, the method including determining the source for each channel by: a) computing the sum of the number of channels carried by the current and all preceding sources, b) computing a source identifier for each channel based on the computed sum of the number of channels carried by the current and all preceding sources, determining which section of the source the channel is located based on the computed source identifier, and determining the destination for each channel by: a) computing the sum of the number of channels carried by the current and all preceding destinations, and b) computing a destination identifier of the first channel sent to each destination based on the computed sum of the number of channels carried by the current and all preceding destinations.

Abstract: The invention is directed to a digital isolation system including an isolation barrier, a transmitter circuit receiving an input signal and transmitting a positive pulse upon detecting a first type of edge in the input signal and transmitting a negative pulse upon receipt of a second type of edge in the input signal and a receiver circuit receiving the transmitted signals, removing noise in the received signal and reconstructing the input signal using a differential comparator.

Abstract: A measurement signal from a detector may have a complementary polarity. For example, an RF power detector may generate an output signal that decreases in magnitude in response to an increasing input signal. In one embodiment, the RF power detector may include a series of transconductance detector cells arranged to progressively turn off as the input signal becomes progressively larger.

Abstract: In one aspect, a resistor process invariant transconductor is provided. The transconductor comprises a voltage input configured to receive at least one voltage signal, a current output configured to provide at least one current signal, wherein a ratio between the at least one voltage signal and the least one current signal forms a total transconductance for the transconductor, and a circuit including at least one integrated resistor connected between the voltage input and the current output, the circuit adapted to maintain the total transconductance substantially constant across variation of the at least one integrated resistor.

Abstract: A multistage dual logic level voltage translator for translating both high and low input logic levels to higher levels, at least one of which levels is above the maximum recommended voltage of transistors implementing the stages, includes an input stage for receiving input logic levels and an output stage including a high voltage converter having at least a pair of cross-coupled converter transistors responsive to the input stage and including a pair of clamping circuit connected one across each of the converter transistors, for providing the shifted low and high output logic levels.

Abstract: A crystal oscillator with variable gain and variable output impedance inverter system includes an inverter, a variable impedance feedback circuit, connected between the output and input of the inverter, a crystal oscillator system, having a crystal with first and second electrodes connected across the input and output of the inverter; a serial variable impedance circuit connected between the inverter output and an electrode of the crystal and a control circuit for temporarily, during start up mode, increasing the impedance of the feedback circuit and decreasing the impedance of the serial circuit relative to the stationary mode impedances and then returning the feedback impedance to the lower impedance level and the serial circuit to the higher impedance level that promotes high frequency stability of the oscillator in the normal, stationary mode, of operation.