Abstract: A power converter provides power across an isolation barrier, such as through the use of coils. A coil driver has transistors connected in a positive feedback configuration and is coupled to a supply voltage in a controlled manner by measuring the output power and opening or closing a switch as needed between the power supply and the coil driver. An output circuit, such as a FET driver, can be used with or without isolation to provide power and a logic signal.

Abstract: A galvanically isolated charge balance system for a multicell battery includes a balancing circuit associated with each cell; each balancing circuit including a flying capacitor; a variable conductance switch; and a biasing circuit for the variable conductance switch; and a galvanically isolating MEMS switching device for selectively connecting the flying capacitor to a voltage supply to charge it to a predetermined voltage and to the biasing circuit for setting the variable conductance switch to adjust the charge on its associated cell to a preselected level.

Abstract: A thin film composition is made from silicon, an insulator such as alumina or silicon dioxide, and at least one additional material such as chromium, nickel, boron and/or carbon. These materials are combined to provide a thin film having a ? of at least 0.02 ?-cm (typically 0.02-1.0 ?-cm), and a TCR of less than ±1000 ppm/° C. (typically less than ±300 ppm/° C.). A sheet resistance of at least 20 k?/? may also be obtained. The resulting thin film is preferably at least 200 thick, to reduce surface scattering conduction currents.

Abstract: A circuit includes a pair of input transistors configured as a differential pair and having input terminals configured to receive an input voltage. The circuit also includes a first current source connected to and configured to provide a first tail current to the pair of input transistors, the first tail current being a class-A current having a non-zero quiescent value. The circuit also includes a second current source connected to and configured to provide a second tail current to the pair of input transistors, the second tail current being a class-B current having a zero quiescent value and a non-zero non-quiescent value. The second current source is configured to provide the second tail current as a function of the input voltage.

Abstract: Bridge structures provide a surface on which to form interconnections to components through through-hole vias. The bridge structures at least partially, and preferably fully, span the gap between two wafers, and, more specifically, between a through-hole via in one wafer and a corresponding component on the other wafer. Bridge structure may be formed on the wafer having the through-hole via and/or the wafer having the component.

Abstract: An amplifier structure includes shield conductors that are provided spatially adjacent to elongated feedback signal lines that couple a feedback circuit to an amplifier input. The shield conductors are provided between the feedback signal lines and a ground plane, which interrupts a parasitic capacitance that otherwise would be established between the feedback signal line and ground. The shield conductors are electrically coupled to the amplifier's outputs which create a capacitance between the output terminal and the feedback signal line. In some embodiments, the capacitance generated between the output terminal and the feedback signal line can suffice as a capacitor in a feedback path of the amplifier and be contained in an integrated circuit die on which the amplifier is manufactured. Optionally, a structure may be provided that eliminates common mode signals on the feedback lines while simultaneously preserving the common mode signals on the amplifier output terminals.

Abstract: Systems and methods for amplitude compressing a digital signal. An input signal is divided into frames having a first and second sets of samples. The samples in the second set are also in a subsequent frame. Peak values are determined for the first and second sets. One or more slopes are calculated based on the peak values. The slopes are used to define a scale factor which is applied to the first set to produce the output signal. For example, if the first peak value exceeds an amplitude threshold, first and last samples in the first set to exceed the amplitude threshold are found. Slopes are calculated for each of three regions of the first set demarcated by the first and last samples. In each region a slope is selected. These slopes along with an initial scale factor are used to calculate the scale factor.

Abstract: A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.

Abstract: An analog to digital converter having improved differential non-linearity is provided. The converter has a memory which is used to look up the actual weight or a weight error corresponding to the bits that have been kept as part of the SAR process to form an output correction value A part of this, for example a residue (the part following the decimal point in a decimal representation) is used to drive a correction DAC which causes a correction to be applied to the trial value presented to a comparator used by the ADC.

Abstract: A bandgap voltage reference circuit that can be implemented with low noise characteristics is described. To achieve such low noise, a bandgap reference circuit is provided that includes an amplifier coupled at its inputs to first and second transistors respectively, the transistors being arranged to generate a voltage representative of the base emitter voltage differences between each of the first and second transistors across a sensing resistor. The circuit additionally provides an additional current to the sensing resistor to reduce the noise contribution into the amplifier from the first transistor. Such a circuit may be corrected for second order temperature effects by inclusion of a temperature dependent current source.

Abstract: An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A protective encapsulant layer covers the top surface of the die substrate. A sensor aperture over the package sensor provides access for the package sensor to the environmental parameter.

Abstract: Disclosed is a method and circuit for dissipating injected parasitic charge including a circuit stage, a pulse generating circuit and a switch. The circuit stage having an input node and an output node that injects a parasitic charge when switched OFF to the output node. The pulse generating circuit can generate a pulsed signal having an input for receiving a control signal. The control signal indicates the circuit stage is switching OFF, and has an output for outputting a pulsed signal in response to the control signal at the input. The pulsed signal can have a predetermined duration. The switch can be configured to be actuated by the pulsed signal output by the pulse generating circuit, and having a terminal connected to the output node of the circuit stage and a terminal connected to circuit to substantially dissipate the injected parasitic charge.

Abstract: A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths.

Abstract: In one aspect, an apparatus for data conversion is provided.

Abstract: A thin film resistor (5) of an integrated circuit comprises an elongate resistive film (7) extending between electrical contact pads (10,11). A low impedance element (20) overlays and is electrically coupled to a portion of the resistive film (7) in an intermediate portion (22) thereof adjacent a second side edge (17) of the resistive film (7) for conducting current in parallel with the intermediate portion (22), and for reducing current density in the intermediate portion (22). First and second transverse edges (28,29) formed by spaced apart first and second slots (26,27) which extend from a first side edge (16) into the resistive film (7) define with a first side edge (16) of the resistive film (7) and the low impedance element (20) first and second trimmable areas (30,31) in the intermediate portion (22).

Abstract: A bandgap voltage reference circuit with an inherent curvature correction which comprises an amplifier having an inverting terminal, a non-inverting terminal and an output terminal is described. A first and second bipolar transistor operable at different current densities are provided each of the transistors being coupled to a corresponding one of the inverting and non-inverting terminals of the amplifier such that a ?Vbe is reflected across a first load element. A current biasing circuit is provided which includes a semiconductor device coupled to each of the first and second bipolar transistors and is configured for applying a non-linear bias current to the first and second bipolar transistors for biasing thereof.

Abstract: A bias current generator for generating bias current is described. The generator comprises an amplifier having an inverting input, a non-inverting input and an output. A first bipolar transistor is associated with one of the inverting and non-inverting inputs of the amplifier. A load MOS device is associated with the other one of the inverting and non-inverting inputs of the amplifier. The load MOS device is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance ron. The first bipolar transistor and the load MOS device are arranged such that a voltage derived from the first bipolar transistor is developed across the drain-source resistance ron of the load MOS device thereby generating a bias current.

Abstract: A reference voltage circuit which is less dependent on semiconductor process variations compared to bandgap based reference voltage circuits. The circuit comprises a first amplifier having an inverting input, a non-inverting input and an output. A current biasing circuit provides first and second PTAT currents, and a CTAT current. The CTAT current is equal in value to the second PTAT at a first predetermined temperature and opposite in polarity. A first load element is coupled to the non-inverting input of the first amplifier and arranged for receiving the first PTAT current such that a PTAT voltage is developed across the first load element. A feedback load element is coupled between the inverting input and the output of the amplifier for receiving the summation of the CTAT current and the second PTAT current.

Abstract: A bandgap voltage reference circuit which provides a bandgap reference voltage without requiring a resistor. The circuit comprises an amplifier having an inverting input, a non-inverting input and an output. First and second bipolar transistors are provided which operate at different current densities each coupled to a corresponding one of the inverting and non-inverting inputs of the amplifier. A load MOS transistor of a first aspect ratio is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance ron. The load MOS device is operably coupled to the second bipolar transistor such that a base-emitter difference (?Vbe) resulting from the collector current density difference between the first and second bipolar transistors is developed across the drain-source resistance ron, of the load MOS device. A cascoded MOS device of a second aspect ratio is operably coupled to the load MOS device and is driven by the amplifier to operate in the triode region.

Abstract: A method of capturing an event in a MEMS accelerometer stores acceleration data in memory, detects a trigger event based on the acceleration data, and modifies a configuration of the memory so that a specified amount of the acceleration data is saved. A MEMS event capturing system includes an inertial sensor having sensor circuitry and event capturing circuitry implemented with the sensor circuitry. The event capturing circuitry includes memory capable of storing acceleration data received from the inertial sensor and a detection module operatively coupled with the memory that detects a trigger event. The event capturing circuitry also includes a management module operatively coupled with the memory and the detection module that modifies the memory's storage configuration when the trigger event is detected.