Abstract: A transconductance cell includes a positive rail for providing a positive power supply voltage and a negative rail for providing a negative power supply voltage. A pair of voltage inputs, one inverting and one non-inverting, develop a differential voltage input signal having a common mode voltage range from one of the rail voltages to within a volt or less of the other rail voltage. And a pair of cross-coupled transconductor circuits each have: (i.) a source voltage follower responsive to one of the voltage inputs for sourcing relatively unbounded output current at unity voltage gain, (ii.) a sink voltage follower responsive to the other voltage input for sinking unbounded output current to a current output terminal, and (iii) a transconductance resistor connected between the source voltage follower and the sink voltage follower for developing a differential output current proportional to the differential voltage input signal.

Abstract: The application provides a switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal.

Abstract: An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (VREF). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled VREF signal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same VREF noise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.

Abstract: A transformer-based power conversion system includes a primary coil is provided in a current path that includes a single energy switch. An oscillator is coupled to a control input of the energy switch. The design conserves switch-based losses as compared to prior designs because a single switch is provided in a current path occupied by the primary coil. The design also provides improved conversion efficiency because parasitic capacitances associated with the energy switch cooperate with charge transfers generated by the oscillator.

Abstract: A microphone system has a base coupled with first and second microphone apparatuses. The first microphone apparatus is capable of producing a first output signal having a noise component, while the second microphone apparatus is capable of producing a second output signal. The first microphone apparatus may have a first back-side cavity and the second microphone may have a second back-side cavity. The first and second back-side cavities may be fluidly unconnected. The system also has combining logic operatively coupled with the first microphone apparatus and the second microphone apparatus. The combining logic uses the second output signal to remove at least a portion of the noise component from the first output signal.

Abstract: In an output stage of an operational amplifier, first and second transistors each provide a collector current under quiescent conditions to first and second current sources. A resistor receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor provides a quiescent current having a value calculated as a function of the resistor voltage and a base-emitter voltage of the second transistor.

Abstract: In a micromachined devices having a movable shuttle driven in oscillation, measuring the electrical charge accumulated on opposing drive capacitors to determine the displacement of the movable shuttle. Alternately, in such a micromachined device, measuring the electrical charge accumulated on a drive capacitor and comparing the measured electrical charge to a nominal electrical charge to determine the displacement of the movable shuttle.

Abstract: A spaced, bumped component structure including a first plate, a second plate spaced from the first plate by a first gap, a plurality of solder bumps interconnecting the plates and defining the first gap; at least one of the plates having an anomalous section including one of a raised platform and recess for defining a second gap having a different size from the first gap.

Abstract: A single-instruction multiple-data processor comprises at least two multiply-accumulator units and associated coefficient memories and data memories. Coefficient memory addresses are formed from a base address and data samples stored in the data memories.

Abstract: An analog to digital converter comprising a conversion engine having redundancy therein; and a dither device for applying a dither to the conversion engine; and a controller adapted to operate the conversion engine to perform a successive approximation conversion of the analog input, and wherein the dither is removed prior to completion of the analog to digital conversion.

Abstract: A MEMS apparatus has a MEMS device sandwiched between a base and a circuit chip. The movable member of the MEMS device is attached at the side up against the circuit chip. The movable member may be mounted on a substrate of the MEMS device or formed directly on a passivation layer on the circuit chip. The circuit chip provides control signals to the MEMS device through wire bonds, vias through the MEMS device or a conductive path such as solder balls external to the MEMS device.

Abstract: A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.

Abstract: A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.

Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.

Abstract: A bipolar differential output circuit includes an input differential bipolar stage for receiving an input signal and generating a differential output current. An output differential pair of bipolar transistors without a bipolar tail current source responds to the input signal by providing a representative output signal. And a current mirror circuit passes current from the input differential pair to the output differential pair.

Abstract: The invention is directed to an interface circuit for bridging voltage domains. The interface circuit receives an input signal, having a larger voltage domain, and safely provides the signal to an electronic device which has a smaller voltage domain. The interface circuit may include a transistor configured as a source follow so that an output of the transistor follows the input of the transistor. A blocking voltage may be provided at the input of the transistor to provide a voltage bias, blocking a range of input voltages to the transistor. The transistor may also have a blocking voltage at a drain terminal of the transistor, to block any output voltage above the blocking voltage.

Abstract: Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.

Abstract: An electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of a complimentary common-drain output stage, at least one diode-coupled transistor inserted between transistors of the output stage, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide gate voltages to the output stage to establish top and bottom reference voltages about the diode-coupled transistor that are spaced from a common-mode voltage. This reference structure maintains a constant output current as the span between the top and bottom reference voltages is selectively altered. In different embodiments, the diode-coupled transistor is replaced with a bipolar junction transistor.