Abstract: A method of estimating a change of a variable over a measurement window, comprising the steps of taking multiple samples of the variable during the measurement window, defining a weight to be associated with each sample, the weight varying as a function of position of the sample within the measurement window, processing the samples taking account of their weight to form an estimate of the change in the variable.
Type:
Application
Filed:
March 19, 2007
Publication date:
February 28, 2008
Applicant:
Analog Devices, Inc.
Inventors:
Robert John Brewer, Michael C.W. Coln, Alain V. Guery, Colin G. Lyden
Abstract: A system and method are provided for determining whether a chipping code from a group of codes is used in a signal. In one embodiment of the invention, a signal is received and each code from the group is correlated with the received signal. The ratio of the highest correlation value to the second highest correlation value is calculated. If the ratio exceeds a threshold, the chipping code may be determined as the chipping code used in the signal. In another embodiment, the ratio of the highest correlation value and the total received power of the signal is calculated. If the ratio exceeds a threshold, the chipping code may be determined as the chipping code used in the signal.
Abstract: A digital signal processor performs despread decoding in wireless telephone systems. Orthogonal codes are used to combine data signals into one overall coded signal which is transmitted. The orthogonal codes are used to retrieve individual data signals from the transmitted overall coded signal. Despread instructions are included in the digital signal processor functionality.
Type:
Grant
Filed:
August 6, 2001
Date of Patent:
February 19, 2008
Assignee:
Analog Devices, Inc.
Inventors:
Rasekh Rifaat, Zvi Greenfield, Jose Fridman
Abstract: A hybrid matching system is disclosed for use with a transmitter and receiver. The hybrid matching system includes a pair of transmitter output nodes for providing a differential transmitter signal for transmission, a pair of receiver input nodes for receiving a differential received signal, a pair of line terminals to interface with a transmission line. The system also includes a first transformer having a first set of windings and a second set of windings, and a second transformer having a first set of windings and a second set of windings. The first set of windings of the first transformer is coupled to the transmitter output nodes. The second set of windings of the first transformer is coupled to the first set of windings of the second transformer. The second set of windings of the second transformer is coupled to the pair of line terminals.
Abstract: A digital processor with a cache that provides fast and low power operation. The cache contains a tag array and a data array. The tag array indicates whether a value is stored in the cache for a particular external address. Access to the data array is necessary to determine the actual value. Access of the data array overlaps access to the tag array. Access to the data array includes a step in which the charge stored on column lines corresponding to multiple ways within the data array is altered based on information stored in the memory. This step occurs while the tag array is being operated. Access to the data array includes a second step of sensing one of the state of charge on a selected column line. Sensing occurs after the value has been read from the tag array and the value in the tag array is used to indicate which, if any way in the data array to sense.
Abstract: Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit.
Abstract: Rather than increasing the mass of the structure, the structure in a sensor system suspends its substrate from some mechanical ground. Motion of the substrate relative to the mechanical ground thus provides the movement information. To those ends, the sensor system includes a base, a substrate, and a flexible member suspended from at least a portion of the substrate. At least a portion of the flexible member is capable of moving relative to at least a portion of the substrate. In addition, the flexible member is secured to the base, thus causing the substrate to be movable relative to the base. Moreover, the mass of the substrate is greater than the mass of the flexible member. The substrate and flexible member are configured to interact to produce a motion signal identifying movement of the base.
Type:
Grant
Filed:
February 15, 2005
Date of Patent:
February 5, 2008
Assignee:
Analog Devices, Inc.
Inventors:
John R. Martin, Timothy J. Brosnihan, Michael W. Judy, Xin Zhang
Abstract: The invention provides a sensor element formed in a first substrate and at least one optical element formed in a second substrate, the first and second substrates being configured relative to one another such that the second substrate forms a cap over the at least one sensor element, the at least one optical element being configured to guide incident radiation on the cap to the at least one sensor element.
Type:
Grant
Filed:
January 26, 2005
Date of Patent:
February 5, 2008
Assignee:
Analog Devices, Inc.
Inventors:
Eamon Hynes, Edward John Coyne, William A. Lane
Abstract: A method for deriving a synchronisation signal (35) from a video signal comprises tracking the blanking level (107) of the video signal with first and second slice level signals (26, 27) and tracking the sync tip level (110) of the horizontal sync signal (109) of the video signal with third and fourth slice level signals (28,29) for determining the blanking level (107) and the sync tip level (110). A value for an intermediate slice level signal (30) is computed from the first, second, third and fourth slice level signals (26, 27, 28, 29) so that the value of the intermediate slice level signal (30) lies approximately halfway between the blanking level (107) and the sync tip level (110).
Abstract: A dynamically read fuse cell includes a first circuit which includes a known reference resistance Rref, and a second circuit which includes a programmed fuse having a resistance Rfuse; the state of the programmed fuse is to be read. The first and second circuits receive a common “read” signal, and are arranged to produce first and second outputs which begin changing state in response; the first and second outputs have respective slew rates which vary with Rref and Rfuse, respectively. The first and second circuits are interconnected such that causing both outputs to begin changing state in response to the “read” signal triggers a time domain race condition, the result of which indicates which of the outputs slewed more quickly in response to the “read” signal, thereby indicating the relationship between Rref and Rfuse and, when Rref is properly chosen, the state of the fuse.
Abstract: A squaring cell combines first and second exponential currents to approximate square law behavior. The exponential currents can be generated by current stacks having pairs of series-connected junctions. The exponential currents can be altered to change the shape of the exponential currents to better approximation true square law behavior. A multiplier combines four exponential currents to approximate a multiplication function. The exponential currents in the multiplier can be generated by current stacks that are cross-connected so as to generate two output currents, the difference of which represents the multiplication of two input signals.
Abstract: A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15).
Type:
Application
Filed:
July 27, 2006
Publication date:
January 31, 2008
Applicant:
Analog Devices, Inc.
Inventors:
Brian Anthony Moane, Colm Patrick Ronan, John Towmey
Abstract: An apparatus for biasing a transistor, comprising: a controllable bias generator; a test circuit; a digital Mth order differentiator responsive to an output of the test circuit; and a controller responsive to the digital Mth order differentiator for controlling the controllable bias generator; wherein the test circuit is configured to calculate an Lth order derivative of the transistor's performance.
Abstract: A signal processing system has a first, digitally controlled, gain element, a second, analogue controlled, gain element and a gain control unit configured to receive a gain request signal and to generate a first gain control signal to be input to the first gain element and a second gain control signal to be input to the second gain element such that the gain provided by the signal processing system corresponds to the gain request signal.
Abstract: Variable attenuation systems having continuous input steering may be used to implement vector or quadrature modulators and vector multipliers. Discrete implementations of attenuators with continuous input steering may have two outputs which may be cross-connected to provide four-quadrant operation. A symmetrically driven center tap may provide improved zero-point accuracy.
Abstract: A successive approximation analog to digital converter comprising a plurality of capacitors which during a successive approximation conversion are selectively connectable to a first reference or a second reference under the command of a controller, wherein during a conversion step where the connections of a given capacitor may be varied the switches to the given capacitor are both placed in a high impedance state during a decision period of a comparator.
Abstract: A MOS isolation coupler is formed on a semiconductor chip by a CMOS process and comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer.
Type:
Grant
Filed:
November 21, 2003
Date of Patent:
January 15, 2008
Assignee:
Analog Devices, Inc.
Inventors:
James Anthony Power, Michael Anthony O'Neill, Colin Gerard Lyden
Abstract: A sensor has a die (with a working portion), a cap coupled with the die to at least partially cover the working portion, and a conductive pathway extending through the cap to the working portion. The pathway provides an electrical interface to the working portion.
Type:
Application
Filed:
August 9, 2007
Publication date:
January 10, 2008
Applicant:
ANALOG DEVICES, INC.
Inventors:
Lawrence Felton, Kieran Harney, Carl Roberts
Abstract: A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency; the phase locked loop including a frequency divider, an interpolator responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to on average, the input fraction; and a timeout circuit responsive to the reference frequency for generating an output a predetermined time after updating to initialize the interpolator in each synthesizer to the same start conditions for locking together the phase of the frequency outputs of all of the synthesizers at the updated frequency.
Abstract: A technique to provide a cost effective solution to detect teletext data that can reduce detected error in teletext when the transmission data rate is known. In one example embodiment, this is accomplished by detecting data bits in an unsynchronized digital data stream by finding start of each data bit based on an estimated data bit width and transitions in the unsynchronized digital data stream.
Type:
Grant
Filed:
January 9, 2004
Date of Patent:
January 8, 2008
Assignee:
Analog Devices, Inc
Inventors:
Amogh D. Thaly, Nilesh Bhattad, Rajesh Bhaskar, Sudheesh A S