Abstract: A DC to DC converter comprising an inductor, first and second electronically controllable switches and a controller, wherein the first electronically controlled switch is interposed between an input node and a first terminal of the inductor and the second electronically controllable switch extends between a second terminal of the inductor and the ground and where a first rectifier extends between the ground and the first terminal of the inductor and a second rectifier connects the second terminal of the inductor to an output node, wherein the controller controls the operation of the first and second switches to perform voltage step down or voltage step up, as appropriate, to achieve a desired output voltage; and wherein the controller is arranged such that the order in which the first and second switches are operated is maintained irrespective of whether the converter is stepping up the input voltage or stepping down the input voltage.

Abstract: A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.

Abstract: A continuous time ?? modulation system with automatic timing adjustment includes a loop filter having continuous time elements for receiving an input; and an ADC for sampling the output from the loop filter in response to an ADC clock; a DAC responsive to the output from the ADC for feeding back an input to the loop filter in response to a DAC clock; a timing measurement circuit for detecting a difference in the timing of the ADC sampling time and the DAC update time and a timing adjustment circuit responsive to the timing measurement circuit for adjusting the timing of at least one of the DAC and ADC clocks for aligning their respective update and sampling times.

Abstract: A DAC circuit is provided which implements a buffered DAC input where the buffer is provided by a differential amplifier whose supply rail is correlated with the input to the DAC. In this way it is possible to buffer the circuitry using amplifiers whose open loop gain specifications may be relaxed without affecting the linearity performance of the DAC.

Abstract: The invention provides a multi-channel DAC circuit which provides for correlation between selected ones of the multiple channels such that a single set of calibration coefficients may be used for calibration of multiple channels.

Abstract: Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.

Abstract: A calibratable analog-to-digital converter system with a split analog-to-digital converter architecture including N Analog-to-Digital Converters (ADCs) each configured to convert the same analog input signal into a digital signal. Calibration logic is responsive to the digital signals output by the N ADCs and is configured to calibrate each of the ADCs based on the digital signals output by each ADC.

Abstract: A variable gain amplifier includes an attenuator having a plurality of pairs of tap points, and a plurality of pairs of gm cells, wherein each pair of gm cells is coupled to a corresponding pair of the tap points, and each pair of gm cells is constructed and arranged to operate as a multi-tan h cell.

Abstract: A logarithmically-responding circuit includes a differential-input amplifier that drives the control terminal of a three-terminal device that exhibits an exponential response in its output current. This arrangement allows the third terminal to be grounded. In a preferred embodiment the three-terminal device is a bipolar junction transistor (BJT). This, and other supporting circuit features described, enable single-supply, wide-range, fully temperature-compensated operation. A compensation technique significantly reduces errors caused by the finite ohmic emitter resistance of a BJT. To support use in logarithmically compressing the current generated by a photodiode, an adaptive bias signal can provided which maintains an essentially constant bias on the photodiode's internal junction.

Abstract: Complex sound events are created by generating multiple different kinds of simpler sounds with randomly varying repetition rates. The average repetition rate can also be variable. The values of sound parameters such as wave selection, pitch distribution, pan distribution and amplitude distribution can have random distributions, as determined by various control inputs, some of which have their own random distributions.

Abstract: Methods and structures are provided for generating a digital display signal in response to an analog display signal whose amplitude varies at a pixel rate and in response to a synchronization signal that defines spatial order for the analog display signal. The structures include a transform generator for providing a Fourier transform of the digital display signal and a transform analyzer which generates frequency and phase control signals in respective response to the frequency of an error spectral component and amplitudes of image spectral components in the transform. The frequency and control signals are applied to respectively adjust the sample rate of the sample clock and alter the phase of the sample clock.

Abstract: A novel clock control circuit completely removes the inter-symbol interference (ISI) in the DAC output waveform without any significant increase in power consumption and silicon area of the DAC. The novel circuit does not increase the requirement for slew rate and bandwidth of the amplifier.

Abstract: A calibration system for a communication system is provided featuring a transmitter circuit, a receiver circuit, a transmission medium having a transfer function for transmitting a signal between the transmitter and receiver circuits, and a calibration system responsive to the altered reference signal of the transmitter circuit for adjusting the reference signal level of one of the transmitter and receiver circuits to compensate for variations in the transmission signal due to the transfer function.

Abstract: A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said seco

Abstract: An efficient approach to generating the bias resulting during the joint equalization/decoding of a Complementary-Code-Keying (CCK) based system is provided that includes a bias generator system having a plurality of inputs responsive only to feedback filter coefficients, the bias generator generating, based upon said feedback filter coefficients, a plurality of output signals corresponding to the bias of a Fast Walsh Transform system for cancelling the bias.

Abstract: Methods and apparatus for reducing the thermal noise integrated on a storage element are disclosed. One embodiment of the invention is directed to a sampling circuit comprising a sampling capacitor to store a charge, the sampling capacitor being exposed to an ambient temperature. The sampling circuit further comprises circuitry to sample the charge onto the capacitor, wherein thermal noise is also sampled onto the capacitor, and wherein the circuitry is constructed such that the power of the thermal noise sampled onto the capacitor is less than the product of the ambient temperature and Boltzmann's constant divided by a capacitance of the sampling capacitor. Another embodiment of the invention is directed to a method of controlling thermal noise sampled onto a capacitor. The method comprises an act of independently controlling the spectral density of the thermal noise and/or the bandwidth of the thermal noise.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull operation. According to some embodiments, the switched capacitor buffer displays an optimal combination of design simplicity, low power consumption and high-frequency response.

Abstract: A flip around amplifier circuit is provided that includes an amplifier having first and second amplification stages, a Miller capacitor, and a resistive element in series with the Miller capacitor, where an output line of the second amplification stage can be coupled to an output line of the first amplification stage through the Miller capacitor and the series resistive element. The circuit can include a feedback capacitor having a first plate coupled to an input line of the amplifier, and a flip around switch that can be operated so as to connect an output line of the amplifier to a second plate of the feedback capacitor. The circuit's classical transfer function can include a zero associated with the Miller capacitor and the series resistive element, and a pole associated with the feedback capacitor and the on-resistance of the flip around switch, where the zero is substantially equal to the pole.

Abstract: An N-phase switching voltage regulator includes N current sensing elements which carry respective phase currents. The voltages present at the switch node sides of the sensing elements are summed and presented to an amplifier which also receives the regulator's output voltage, to produce an output which is proportional to the regulator's total output current Iout. The invention also provides a means for direct insertion of total inductor output current information into a regulator's voltage-mode control loop, to provide active voltage positioning (AVP) for the output voltage. A voltage based on total inductor output current is summed with the regulator's reference voltage; this sum and Vout are applied to the voltage control error amplifier, the output of which is processed to operate the regulator's switches. This enables the regulator's output to have a desired droop impedance and to provide AVP of Vout as a function of total filtered inductor output current Iout(fltr).