Abstract: A method and a secure mode controller are provided for controlling context switching between secure and user modes in a processing system including a processor and a memory management unit. The method comprises monitoring the memory management unit to detect a non-cache access to an entry point address that contains a secure mode entry instruction, verifying, in response to detection of the entry point address, that the secure mode entry point instruction is executed by the processor, and enabling context switching from the user mode to the secure mode in response to verifying that the secure mode entry instruction is executed by the processor. Each cache line of an instruction cache and a data cache may have a tag containing a secure bit to identify a secure cache line or a non-secure cache line.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. Channel control logic controls transfer of data through the DMA channels in response to parameters contained in at least one DMA descriptor having a programmable format.

Abstract: In a first embodiment of the invention there is provided an electronic chip for use with an automatic testing equipment device testing a device under test. The device under test has a plurality of pins and the electronic chip is placed in a channel of a test card that is associated with one of the pins. An input signal is provided to a pin of the device under test and the resulting output is provided to the pin electronics for the channel of the test card. In most embodiments, the output signal is a voltage signal. One purpose for the electronic chip is to measure jitter based upon timing measurements performed by the electronic chip. Jitter measurements are particularly important for high-speed serial devices. The electronic chip includes an integrating time measurement circuit for receiving the input signal and producing an output signal including a timing measurement of at least a portion of the input signal.

Abstract: A homodyne receiver is provided for receiving GSM and UMTS transmissions. The receiver may also be used for other transmission schemes. The receiver includes an electronically reconfigurable low pass filter and an off set generator for providing DC offset correction for offsets which may be generated as a result of coupling between a local radio frequency oscillator and the receiver front end.

Abstract: A wireless terminal circuit includes a variable high frequency clock oscillator that provides a high frequency clock signal and a fixed low frequency clock oscillator that provides a low frequency clock signal. A phase-locked loop adjusts a ratio of the frequency of the high frequency clock signal to the low frequency clock signal by adjusting the frequency of the high frequency clock signal. The phase locked loop includes a divider for dividing the high frequency clock signal, the divide ratio of which divider is controlled by a sigma-delta modulator. A wireless terminal local oscillator calibration circuit includes a frequency control circuit including both the high frequency clock oscillator and the low frequency clock oscillator.

Abstract: An interpolated variable gain amplifier (VGA) utilizes multiple active feedback cells. The active feedback cells may be implemented as transconductance (gm) cells that replicate gm cells in the interpolated input stages.

Abstract: A small signal amplifier with a large signal output boost stage are connected between first and second supply rails. The small signal amplifier receives first and second input signals and provides an output signal at an output node which drives a load. Under small signal conditions, the output signal varies approximately linearly with the difference voltage. However, under large signal conditions, a rail-to-rail large signal output boost stage connected to the output node is arranged to drive the output node close to the first or second supply rail as needed to provide the current demanded by the load. The large signal output boost stage is off in small signal conditions, but comes on rapidly and transfers maximum charge to the load under large signal conditions.

Abstract: A multimode fiber system includes a transmitter for transmitting an optical signal and a receiver that receives the optical signal. At least one mode filter is coupled between the receiver and the transmitter and passes only a specific set of fiber modes from the transmitter to be received by the receiver. The at least one mode filter comprises a tapered core section that includes a double taper configuration joined at the narrowest regions and in which each end of the two tapers has dimensions compatible with the fiber at that end.

Abstract: An inertial sensor includes at least one pair of sensor elements arranged in a linear array. Each sensor element has a frame and a movable mass suspended within the frame. The frames of each pair of sensor elements may be coupled so that the frames are allowed to move in anti-phase to one another along parallel axes but are substantially prevented from moving in phase with one another.

Abstract: A galvanically isolated signal conditioning system includes a signal conditioning circuit on an integrated circuit chip; a flying capacitor; and a galvanically isolating MEMS switching device on an integrated circuit chip for selectively switching the flying capacitor from across a pair of input terminals in one state to across the input terminals of the signal conditioning circuit in another state.

Abstract: A transistor cell is provided that includes transistors arranged to turn on for different voltages applied to a control terminal of the transistor cell. The transistor cell can include a first transistor having a gate, a source, and a drain, and a second transistor having a gate, a source, and a drain, wherein the source of the second transistor is coupled to the source of the first transistor, and the drain of the second transistor is coupled to the drain of the first transistor. The transistor cell can further include a first resistor coupled between the gate of the first transistor and the gate of the second transistor. A frequency mixer is also provided that includes at least one transistor cell.

Abstract: A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and frequency down signals that adjust the frequency of the clock signal to be equal to the frequency of the data signal. A step control system is responsive to the rotational frequency detector and a step clock signal and is configured to define predetermined pulse widths for the frequency up and frequency down signals.

Abstract: An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

Abstract: A current driven DAC architecture uses a single resistance string arranged to have a cyclic configuration and a plurality of nodes, one of the nodes being connected to a known potential, e.g., ground potential, and at least two current sources connected to selected ones of said nodes through operable switches, and an output connected to a selected one of said nodes. In one modification, 22n?2 LSB (least significant bit) voltage levels are generated as outputs from 2n cyclic string resistors and two current sources. In another modification, spurious-free resolution of (2n?2) bits and (2n?1) bit resolution with lower SNDR are achieved by using 2n resistors and two current sources. In one described embodiment, 2n unit impedances in the cyclic string result in 2(n?1) bit resolution. Thus, the single cyclic string of resistances achieves the function of both MSB sub-string and LSB sub-string.

Abstract: A programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm includes a Galois field linear transformer system (GFLT) responsive to a first input data block to execute an E permutation to obtain an expanded data block and combine it with a key to obtain a second larger intermediate data block in one cycle; and further includes a parallel look-up table system for implementing the unique data encryption standard selection function(s) and for condensing the second larger intermediate data block to a third data block similar to the first input data block in a second cycle and submitting it to the Galois field linear transformer system to execute a second permutation in a third cycle resulting in a data encryption standard cipher function of the first input data block.

Abstract: The present application addresses the problem arising during the erasure of EEPROMs where the FN tunnelling erase cycle is not self-limiting. Existing methods address this problem by employing monitoring algorithms. However, these algorithms slow the erase procedure time. The present application provides an alternative method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The method comprises the initial step of raising the potential at the erase gate and lowering the potential at the control gate to cause FN tunnelling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a sufficient value to cause to start FN tunnelling through the oxide of the transistor. A new structure particularly suitable for this method is also disclosed.

Abstract: Buffer amplifiers are provided that demonstrate enhanced efficiency because they include current sources which are configured to be switched off during operational modes in which the amplifiers' output signals are not needed. Amplifier embodiments include charge-transfer transistors and filter capacitors that reduce spurious signals which may be generated by the switching operations.

Abstract: A method and apparatus for driving a current switch with a differential drive signal monitors both the temperature of the switch and the current through the switch. The method and apparatus dynamically control the amplitude of the drive signal as a function of the switch temperature and the current through the switch. The result is a significant reduction in base drive amplitude without compromise to offset and linearity performance of the driver. The resulting dynamic performance of the switch is substantially improved.

Abstract: An amplifier output voltage swing extender circuit comprises a differential amplifier powered between first and second power supply rails, which receives first and second input signals at non-inverting and inverting inputs, respectively, and provides an output at a first output node. A level shifting circuit, preferably a voltage divider, is connected in series with the first output node and shifts the node voltage toward the second rail by a fixed amount; the shifted voltage is provided at a second output node. A feedback network couples the second output node voltage to the amplifier's inverting input, such that when a voltage VSET is applied to the non-inverting input, the maximum negative voltage excursion at the first and second output nodes is greater than the value of the VSET voltage with respect to the second supply rail.

Abstract: A technique for allocating fingers in a path searcher of a multipath receiver involves determining a required number of fingers for each multipath region, determining a number of allocated fingers for each multipath region according to an area-based weighting scheme such that each multipath region that is allocated fewer than its required number of fingers is deemed to have a non-zero residual area, allocating any surplus fingers to multipath regions having non-zero residual areas until either no surplus fingers remain or each multipath region is allocated its required number of fingers, and placing any fingers allocated to each multipath region within the multipath region. Placing the fingers in un-resolvable path scenario involves detecting path location at the edges of multipath region; placing fingers at the edges and placing remaining fingers uniformly between the first and the last path such that the there is a minimum placement separation between the fingers.