Abstract: An integrated circuit arrangement clocked by a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, the arrangement comprising: a data transfer buffer for buffering a data stream for transfer between respective first and second ones of said regions, and a data transfer controller, associated with said data transfer buffer and said respective regions, configured to control transfer of said data stream by: initially synchronizing between said respective regions at a start of said data stream, receiving data, in said buffer, from said first region, at a predetermined rate, and outputting said data stream to said second region at said predetermined rate in accordance with said initial synchronization. The arrangement allows deterministic data patterns to arrive at the receiving domain at minimal hardware cost.

Abstract: An integrated circuit is described including internal circuitry and having at least one external connection. A pad cell is electrically interposed between the external connection and the internal circuitry, the pad cell comprising a first group of components adapted to protect the internal circuitry from transients at the external connection and providing, during normal operating conditions of the integrated circuit, a first signal path to the internal circuitry, and a second group of components providing a second signal path from the external connection to the internal circuitry. The second signal path is non-operable during the normal operating conditions but on application of a predefined voltage at the external connection becomes operable.

Abstract: A reconfigurable communication transmitter core includes a digital pulse-shaping filter to perform pulse-shaping operations upon a digital modulated signal and a finite state machine to controls operation and reconfiguration of the digital pulse-shaping filter. A first memory stores coefficients and a second memory stores data. A multiplier multiplies a data value stored in the second memory with a corresponding coefficient value stored in the first memory. An adder adds each multiplication product from the multiplier with the content of an accumulation register wherein the accumulation register accumulates the sum from the adder. A rounding unit rounds off the content of the accumulation register and to provide rounded-off content as an output of the reconfigurable communication transmitter core. The finite state machine reconfigures a look-up table value set in the first memory, the first memory having pre-stored therein pulse shaped filtered waveforms.

Abstract: A digital to analog converter comprising: a digital to analog conversion core adapted to receive at least one reference voltage and a digital word to be converted, and to output an analog voltage as a function of the digital word and the at least one reference voltage; a sensing circuit for sensing a difference between a first ground voltage associated with an output of the digital to analog converter and a ground reference voltage occurring at the digital to analog converter; and a compensation circuit for applying a compensation voltage to the at least one reference voltage used by the conversion core of the digital to analog converter.

Abstract: A microphone includes a diaphragm assembly supported by a substrate. The diaphragm assembly includes at least one carrier, a diaphragm, and at least one spring coupling the diaphragm to the at least one carrier such that the diaphragm is spaced from the at least one carrier. An insulator (or separate insulators) between the substrate and the at least one carrier electrically isolates the diaphragm and the substrate.

Abstract: Methods and structures are provided to improve the transfer functions of analog-to-digital converter systems. They address the converter error function that corresponds to a converter's transfer function. In particular, they provide a corrector with a corrector transfer function that defines a corrector error function which substantially mirrors at least a portion of the converter error function. The corrector processes the converter's output digital signals to realize corrector digital signals which are then combined with the original output digital signals to obtain a system with a system error function that is significantly reduced from the original converter error function.

Abstract: An output stage interface circuit (50) implemented on a P-substrate comprises a first substrate diffusion isolated main NMOS transistor (MN1) coupling a data output terminal (5) to a first rail (2) which is held at ground, and a second main PMOS transistor MP2 coupling the data output terminal (5) to a second rail (3) to which the power supply voltage VDD is applied. First and second data control signals on first and second data control lines (8) and (9) through first and second primary and secondary buffer circuits (11, 14, 12, 15) selectively operate the first main transistor MN1 and the second main transistor MP2 for determining the logic high and low states of the data output terminal (5).

Abstract: A transconductance input apparatus energized by supply voltage has an input for receiving an input signal, and an output for delivering an output signal. The apparatus also has a plurality of transconductance stages for converting the input signal into the output signal, which is substantially free of dead zones when the total supply voltage is 2.7 volts or less.

Abstract: A system and method for scene change detection in a video sequence employing a randomly sub-sampled partition voting (RSPV) algorithm is provided. In the video sequence, a current frame is divided into a number of partitions. Each partition is randomly sub-sampled and a histogram of the pixel intensity values is built to determine whether the current partition differs from the corresponding partition in a reference frame. A bin-by-bin absolute histogram difference between a partition in the current frame and a co-located partition in the reference frame is calculated. The histogram difference is compared to an adaptive threshold. If the majority of the examined partitions has significant changes, a scene change is detected. The RSPV algorithm is motion-independent and characterized by a significantly reduced cost of memory access and computations.

Abstract: A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.

Abstract: In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of the first type that are included in a respective column of pixels, and each array readout line is selectively coupled to at least one of the first column readout lines. In another embodiment, an image sensor includes a pixel array, column readout lines, and array readout lines, wherein the pixel array includes a row of pixels which includes pixels of a first type, each column readout line is selectively coupled to an output of a respective pixel of the first type that is included in the row of pixels, and each array readout line is selectively coupled to at least one of the column readout lines.

Abstract: A method for deinterlacing an interlaced video signal is provided which employs a median single edge based line average field interpolation algorithm. The algorithm employs a median filter to determine whether motion occurred between scanning two fields of an interlaced frame and, based on the results, reconstructing intermediate lines in the display frame. The median performs a median computation by determining whether a target pixel value is a median value, rather than computing the median value and determining whether the target pixel value is equal to the computed median.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.

Abstract: Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write information for the level one memory and for a level two memory. A write buffer is configured to hold write information, received from the store buffer, for the level two memory. The write buffer has a normal capacity and an excess capacity. A memory controller enables the excess capacity of the write buffer when a high priority task is being serviced and inhibits write access to the excess capacity of the write buffer when a high priority task is not being serviced. In other embodiments, the digital signal processor includes first and second fill buffers configured to hold read data in a fill operation. The memory controller steers low priority read data to the first fill buffer or the second fill buffer based on priority of the fill operation.

Abstract: A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.

Abstract: A group metering method (and system) for monitoring electrical energy consumption by a plurality of proximate users replaces multiple individual user-meters by a single electronic meter. A single computational engine computes consumed energy values by the users and deploys a single subsection set (display, real time clock, and non-volatile memory) which can be located on a PCB. The system, usable for single or three phase, may be located out of reach from the users to make it tamper proof. Individual ADCs obtain electrical current values (through current transformers,) of power consumed by individual users and cooperate with a single DSP to compute energy consumption by individual users, readable on a common display in round robin fashion. Differences between the sum of energy values consumed by the users and a consolidated energy reading beyond a known threshold are reported as possible user-tampering. Asynchronous communication ports communicate with display units and AMR modules.

Abstract: A sample rate converter reduces the sampling rate of a signal by a fractional number U/D, where U represents an up-sampling rate and D represents a down-sampling rate. The converter comprises an input for receiving an input data stream at a first rate and an FIR filtering stage. The FIR filtering stage comprises a set of D polyphase filter branches, each branch including a set of filter coefficients which operate on a sample of the input signal. The converter also comprises a commutative switch which selectively connects a sample of the input data stream to one of the polyphase filter branches, the switch being arranged to skip every U?1 filter branches during a cycle through the filter branches. An output outputs an output data stream at a second data rate which is lower than the first data rate.

Abstract: A translation loop modulator for a transmission circuit in a communication system includes an input modulation unit for receiving at least one input signal that is representative of information to be modulated. The input modulation unit also receives a feedback signal, produces an intermediate modulated signal responsive to the input signal and the feedback signal. The modulator also includes a comparator unit that receives the intermediate modulated signal and a reference signal, and produces an output transmission signal responsive to the intermediate modulated signal and the reference signal. The modulator also includes feedback circuitry that is coupled to the output transmission signal, and to the reference signal. The feedback circuitry is also coupled to the input modulation unit and produces the feedback signal responsive to the output transmission signal and the reference signal.

Abstract: A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first

Abstract: Methods and structures are provided to enhance the linearity of amplifiers such as those which include a complementary common-collector amplifier stage. The methods and structures configure this stage so that each transistor of the stage drives an output port through a linearizing resistance. The methods and structures then control a bias current through the stage to substantially be the thermal voltage VT divided by twice the linearizing resistance.