Abstract: A system and method including a DAC that receives a multi-bit digital signal and outputs at least two analog signals including a first analog signal and a second analog signal, the first analog signal being indicative of a sum of values of bits in the multi-bit digital signal, the second analog signal also being indicative of said sum of values of said bits in the multi-bit digital signal. The first and second analog signals may be substantially equal or they may be different from each other.

Abstract: A circuit for a high speed digital multiplexer has an active load circuit connected to an output of the digital multiplexer. The active load circuit loads the multiplexer output with a transimpedance stage with low input resistance to reduce the RC time constant at the multiplexer output. The active load circuit may be based on two active devices connected to the multiplexer output so as to form a differential cascode circuit.

Abstract: Varactor and reference oscillator structures are provided that are particularly suited for integrated circuit fabrication and which provide excellent parameter performance (e.g., monotonicity, linearity, low phase noise and low differential and integral non-linearity) so that they are useful in a variety of wireless communication structures (e.g., cellular telephones).

Abstract: Frequency offsets between a received carrier signal and a receiver's LO frequency are compensated by determining the offset and adjusting the phase of a demodulated signal derived from the modulated carrier. For frequency offsets that produce DC voltage offsets in I and Q components of the demodulated signal, the phase correction is implemented by operating upon the I and Q components with phase rotation operators in the form of sin ? and cos ?, where ? is an angle whose tangent is the result of dividing the Q by the I frequency offsets.

Abstract: Driver circuits and methods for operating driver circuits in automatic test equipment are provided. The driver circuit includes an output circuit operable in a dynamic mode and in a termination mode, and a mode control circuit for supplying a first current to the output circuit in the dynamic mode and for supplying a second current to the output circuit in the termination mode in response to a mode select signal. The mode control circuit may include a current multiplier and a switching circuit for switching a control current supplied to the current multiplier. In one example, the slew current supplied to the output circuit is controlled in response to the mode select signal.

Abstract: A method of producing an integrated MEMS resonator includes providing a substrate including single crystal silicon and partially forming a resonator in a first portion of the substrate, the resonator having a resonating element formed by the substrate and an electrode, the resonating element and the electrode forming a variable capacitor. The method also includes forming circuitry in a second portion of the substrate, the circuitry configured for detecting capacitance of the variable capacitor and finish forming the resonator and integrating the resonator with the circuitry so that the electrode is in communication with the circuitry.

Abstract: A MEMS resonator has an outer element having an inner surface, the inner surface defining an area and a inner element coupled to the outer element and disposed within the area. The MEMS resonator also has an actuation electrode, in communication with the outer element, for generating electrostatic signals that cause the inner element to flex in a periodic manner.

Abstract: A system and method of improving signal to noise ration (SNR) in a fixed point fast Fourier transform (FFT/IFFT) generates from sample inputs and a twiddle factor butterfly outputs for each stage; scales the butterfly outputs of this stage from a predicted normalization scale factor to obtain the maximum butterfly output without overflow from this stage; determines from the butterfly outputs of this stage the minimum normalizing exponent for the butterfly outputs of this stage and predicts a normalization scale factor of the next stage from the minimum normalizing exponent of this stage and a stage guard scale value to obtain the maximum butterfly output without overflow from that next stage.

Abstract: A method of producing an electronic device electrically and mechanically couples an integrated circuit to a leadframe to produce an intermediate assembly. At least a portion of the intermediate assembly then is encapsulated with a molten encapsulating material. After it is encapsulated, the method permits the molten encapsulating material to substantially solidify. A method of detecting the orientation of a sensor as mounted to an external object also is disclosed.

Abstract: A selectable-gain amplifier selectively couples different capacitors and feedback networks to a gain stage to provide operating characteristics that may include constant bandwidth operation. An interpolated VGA includes pairs of gm cells with cross-connected outputs and may include output cascodes. A dual-rank interpolator utilizes a correction current with a second-order temperature characteristic which may compensate for temperature effects in the transistor ranks.

Abstract: Signal converter systems are provided with N analog-to-digital converters that respectively respond to N interleaved clock signals which have a common clock frequency and are further provided with a filter network that processes the converters' output digital sequences with a selected filter passband a filter passband that is contained within a single one of Nyquist zones whose widths are one half of the clock frequency and that is positioned to pass information contained in the analog signal. In a system embodiment, the filter network comprises a symmetric systolic finite impulse response filter arranged to define N input ports for reception of the digital sequences.

Abstract: A logarithmic amplifier is compensated by a feedback loop. The feedback loop may control a series of detector cells in response to an output from one or more of the detector cells. The feedback loop may be used to provide frequency compensation to the log amp by adjusting the bias currents to the detector cells. One detector cell may be arranged to generate a limiting signal while another detector cell is arranged to generate a zero signal. By arranging the feedback loop to adjust the bias cell so as to maintain the difference between the limit signal and the zero signal at a constant value, the output swing of the detector cells is held constant, thereby stabilizing the slope of the log amp.

Abstract: A microphone is formed to have a diaphragm that is configured to improve signal to noise ratio. To that end, the microphone has a backplate having a hole therethrough, and a diaphragm movably coupled with the backplate. The diaphragm has a bottom surface (facing the backplate) with a convex portion aligned with the hole in the backplate.

Abstract: A thin film resistor (5) of an integrated circuit comprises an elongate resistive film (7) extending between electrical contact pads (10,11). A low impedance element (20) overlays and is electrically coupled to a portion of the resistive film (7) in an intermediate portion (22) thereof adjacent a second side edge (17) of the resistive film (7) for conducting current in parallel with the intermediate portion (22), and for reducing current density in the intermediate portion (22). First and second transverse edges (28,29) formed by spaced apart first and second slots (26,27) which extend from a first side edge (16) into the resistive film (7) define with a first side edge (16) of the resistive film (7) and the low impedance element (20) first and second trimmable areas (30,31) in the intermediate portion (22).

Abstract: A chopper-stabilized current-mode instrumentation amplifier comprises first and second input amplifiers coupled to respective input nodes and arranged to produce respective currents in response to a differential input voltage applied to the input nodes; the currents are coupled to an output node. To reduce gain errors that might otherwise arise due to the parasitic capacitances of the on- and/or off-chip devices and/or structures making up the input amplifiers, the invention includes gain correction circuitry coupled to the IA. The gain correction circuitry replicates at least some of the parasitic capacitances, and provides compensation currents to the IA which reduce both input- and output-referred gain errors that might otherwise arise.

Abstract: A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch.

Abstract: A bandgap voltage reference circuit (1) produces a bandgap voltage reference (Vref) on an output terminal (3) relative to a common ground voltage terminal (4). The circuit (1) develops a PTAT voltage across a primary resistor (r3) which is reflected and gained up across an output resistor (r4) and summed with a CTAT voltage to produce the voltage reference (Vref). A first circuit comprising a PTAT voltage cell (15) having first and second transistor stacks of first and second transistors (Q1,Q2) and (Q3,Q4) operated at different current densities develops a PTAT (2?Vbe) across a first resistor (r1). The PTAT voltage developed across the first resistor (r1) is applied to an inverting input of a first op-amp (A1), the output of which is coupled to a first end (9) of the primary resistor (r3).

Abstract: An optical communication system includes a transmitter that receives an input optical signal from an optical source and performs filtering so that an output signal from the transmitter includes a specific set of fiber modes that are allowed to pass for further processing. A receiver receives the output signal and performs the necessary operations to retrieve a signal indicative of the input signal.

Abstract: A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.

Abstract: An anti-cross conduction driver control circuit and method prevent the occurrence of race conditions and avoid cross-conduction between series-connected power devices, typically MOSFETs, controlled in accordance with the present invention. Individual state machines are connected across the inputs and outputs of each power device driver, and are arranged to accurately determine when the driver has completed a task requested of it. Each state machine produces a “lockout” signal based on driver status, which is used to inhibit the operation of the opposite driver under prescribed conditions, and to thereby prevent cross-conduction between the series-connected power devices.