Abstract: A rail-to-rail amplifier suitable for use in a line-inversion LCD grayscale reference generator comprises a p-type differential pair and a first switchable current source which supplies tail current to the p-type pair in response to a first control signal, and an n-type pair and a second switchable current source which supplies tail current to the n-type pair in response to a second control signal; when its tail current is present, each pair provides a differential output current which varies with a differential input signal. A control circuit provides the control signals such that the first switchable current source is enabled when a voltage applied to the amplifier's input is closer to the amplifier's negative supply rail, and the second switchable current source is enabled when the applied voltage is closer to the amplifier's positive supply rail, such that only one input pair is active at any given time.

Abstract: A method for forming an isolation filled trench (25) in a silicon layer (21) of an SOI structure (20). The trench (25) is relieved adjacent its open mouth (30) in order to displace the commencement of bridging of the trench (25) with the filling material, to a level (36) well below a first surface (27) of the silicon layer (21) for in turn displacing voids (35) from the open mouth (30) into the trench (25) below the level (36). The trench may be relieved by forming tapered portions (40) in the side wells (29) adjacent the open mouth (30), and/or by relieving one or more lining layers (32) in the trench (25) adjacent the open mouth (30) to form tapered portion (52) and (53). Instead of relieving the trench (25) by tapering the side walls (29) relieving recesses may be formed into the first surface (27) of the silicon layer (21) adjacent the open mouth (30).

Abstract: In one implementation, a programmable processor is adapted to include a first set of registers and a second set of registers. The first set of registers may have a future file, and the second set of registers may be architectural registers. Following a termination of an instruction in the processor, the future file may be restored with values in the second set of registers. The future file is restored over more than one clock cycle.

Abstract: A correlated double sampling pixel gain amplifier includes an operational amplifier, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal. The feedback capacitor may include a capacitor array.

Abstract: A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture includes a register pair and an alignment multiplexer. Two 32 bit grouped words may be loaded into the register pair. Each grouped word includes four 8 bit operands. The alignment state of the 32 bit words may be determined by the two least significant bits (LSBs) of the pointer addresses of the grouped words. These LSBs are used to control the alignment MUX to select n operands from the two 32 bit grouped words and output an aligned 32 bit grouped word to execution units for parallel processing.

Abstract: The invention recognizes that sampler linearity is degraded because transfer voltage across a sampler's buffer varies with amplitude of the analog signal being sampled. Because this transfer voltage is in the signal path it modulates the signal and distorts the resulting sample. In the invention, sampler embodiments are provided which include replica current generators that provide and route sample currents to sample capacitors so that an associated buffer transistor can transfer a faithful copy of the analog signal's potential to the sample capacitor and thereby significantly enhance the sampler's linearity. The replica current generators generally include a replica load that mimics the sample load driven by the buffer transistor.

Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Abstract: An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

Abstract: A voltage source includes first and second pn junctions which conduct the outputs of respective current sources to establish respective base-emitter voltages Vbe1 and Vbe2 at respective nodes; Vbe1 and Vbe2 can each be generated with a current I or a current N*I. An amplifier A1 has its non-inverting input connected to the second node and its inverting input connected to the first node through an input capacitor; a feedback capacitor is connected between the inverting input and a third node. Switches are connected between A1's inverting input and A1's output, between the third node and A1's output, and between the third node and a circuit common point. A control circuit operates the switches and current sources during first and second operating phases to selectively produce a temperature independent output voltage or a temperature dependent output voltage.

Abstract: A high-speed programmable serial port having a finite state machine, a clock generator capable of controlling shifting of bits from a shift register and a shift register having a bit counter capable of maintaining a numbered count of data bits in a serial output. The clock generator and shift register reduce the burdens on a finite state machine, thus improving data throughput and the ability to provided data according to a multitude of data protocols.

Abstract: An analog to digital converter comprising at least two analog to digital conversion engines and a controller for controlling the operation of the analog to digital conversion engines such that during a first phase of an analog to digital conversion process the engines collaborate such that a plurality of bits can be determined during a single trial step; and during a second phase of the analog to digital conversion the conversion engines work independently; and the controller receives the outputs of at least one of the conversion engines and processes them to provide an output word.

Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitised; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.

Abstract: An electronic memory device includes at least one memory cell, a write circuit that defines an output node and mediates a discharge associated with a write operation flowing to the output node, and a write strength selection circuit that modifies at least one characteristic of the discharge. A method for testing data retention of an electronic memory device includes providing a write circuit, storing a value in at least one memory cell of the memory device, directing a weak write operation to the at least one memory cell, and sensing the memory cell to determine if the stored value changed in response to the weak write operation.

Abstract: A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

Abstract: A common-mode detector includes a first difference amplifier that is connected to compare a first input voltage with a feedback voltage to provide a first result, a second difference amplifier that is connected to compare a second input voltage with the feedback voltage to provide a second result, and a feedback amplifier that is connected to drive the feedback voltage to a level that is substantially the average of the first and second input voltages in response to receiving the first and second results.

Abstract: An integrated circuit is provided in which a scan controller for controlling a scan test is integrated within the integrated circuit and shares the same input pins as a serial programmable interface of the integrated circuit.

Abstract: An isolation system with analog communication across an isolation barrier includes an isolation barrier circuit having at least one isolation element; a digital to analog circuit having an analog output connected to the isolation barrier and an input for receiving an input digital signal to be communicated across the isolation barrier; and an analog to digital circuit having an input coupled to the analog output of the isolation barrier circuit for providing a digital output signal.

Abstract: A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

Abstract: A DAC (1) has a switched element capacitor (7, Cr) to which charge is delivered via switches (6, S1/S2) depending on required analog voltage level (Vref1, Vref2). An output switch (S3) is closed and a ground switch (S4) is opened to deliver charge to the output according to received bi-level digital inputs (+1, ?1). The control block (2) has a memory and determines an inactive output level if there is an input digital transition from +1 to ?1 or from ?1 to +1. For the inactive level S3 is kept open and S4 is kept closed. Thus, for every clock cycle with one of these transitions there is no charge transfer and hence no thermal noise. Overall noise is therefore considerably reduced.

Abstract: An RMS-to-DC converter system is disclosed. The system includes a variable gain amplifier having transfer function ripple that receives an input signal and provides an amplifier output signal, a detector that receives the amplifier output signal and provides a detector output signal, an error amplifier that receives the detector output signal and provides an error amplifier output signal having an AC component, and a feedback circuit coupled to the error amplifier output signal and to the variable gain amplifier for providing a feedback signal to the variable gain amplifier that includes an AC component for reducing transfer function ripple of the RMS-to-DC converter system.